From patchwork Mon Jul 9 10:31:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiraz HASHIM X-Patchwork-Id: 1172241 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id DFAA040B18 for ; Mon, 9 Jul 2012 10:39:36 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SoBJV-0004lA-0v; Mon, 09 Jul 2012 10:35:33 +0000 Received: from eu1sys200aog109.obsmtp.com ([207.126.144.127]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1SoBFa-0004Rd-Rr for linux-arm-kernel@lists.infradead.org; Mon, 09 Jul 2012 10:31:35 +0000 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob109.postini.com ([207.126.147.11]) with SMTP ID DSNKT/qy/fw6ZdfIXhdovEE8sOhcAqWrGGxn@postini.com; Mon, 09 Jul 2012 10:31:30 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id AF07EA7; Mon, 9 Jul 2012 10:23:03 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas2.st.com [10.80.176.10]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A12891AF9; Mon, 9 Jul 2012 10:31:21 +0000 (GMT) Received: from localhost (10.199.82.228) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.192.1; Mon, 9 Jul 2012 18:31:21 +0800 From: Shiraz Hashim To: Subject: [PATCH 5/6] Clk: SPEAr1340: fix sys clock parent source and corresponding mask value Date: Mon, 9 Jul 2012 16:01:05 +0530 Message-ID: <1341829866-26091-5-git-send-email-shiraz.hashim@st.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1341829866-26091-1-git-send-email-shiraz.hashim@st.com> References: <1341829866-26091-1-git-send-email-shiraz.hashim@st.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.127 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Vipul Kumar Samar , spear-devel@list.st.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Vipul Kumar Samar sys_clk have multiple parents and selection of parent is depends on sys_clk_ctrl register (bit no. 23:25) with possible values, 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Update sys_clk parent array accordingly (ex. 0:3-pll1_clk) and fix mask value to 7. Signed-off-by: Vipul Kumar Samar --- drivers/clk/spear/spear1340_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index e69c542..b3b56de 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c @@ -25,7 +25,7 @@ #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27 #define SPEAR1340_HCLK_SRC_SEL_MASK 1 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23 - #define SPEAR1340_SCLK_SRC_SEL_MASK 3 + #define SPEAR1340_SCLK_SRC_SEL_MASK 7 /* PLL related registers and bit values */ #define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210) @@ -369,8 +369,8 @@ static struct frac_rate_tbl gen_rtbl[] = { /* clock parents */ static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; -static const char *sys_parents[] = { "none", "pll1_clk", "none", "none", - "sys_synth_clk", "none", "pll2_clk", "pll3_clk", }; +static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", + "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", }; static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", }; static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",