From patchwork Thu Jul 12 12:58:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 1188881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id EF74C40B20 for ; Thu, 12 Jul 2012 12:56:58 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SpIs0-0007kk-15; Thu, 12 Jul 2012 12:51:48 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SpIlV-0005p7-4U for linux-arm-kernel@lists.infradead.org; Thu, 12 Jul 2012 12:45:07 +0000 Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7100CGQSQVP9C0@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 12 Jul 2012 21:44:58 +0900 (KST) X-AuditID: cbfee61b-b7f566d000005c8a-30-4ffec6ca77f4 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 10.DE.23690.AC6CEFF4; Thu, 12 Jul 2012 21:44:58 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7100BY3SQSXZ10@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 12 Jul 2012 21:44:58 +0900 (KST) From: Thomas Abraham To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/3] ARM: Samsung: Add support for MSHC controller clocks Date: Thu, 12 Jul 2012 18:28:45 +0530 Message-id: <1342097927-25334-2-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1342097927-25334-1-git-send-email-thomas.abraham@linaro.org> References: <1342097927-25334-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAJMWRmVeSWpSXmKPExsVy+t9jAd1Tx/75G2z+oWux6fE1VgdGj81L 6gMYo7hsUlJzMstSi/TtErgyfp/exlxwXbbixsmtLA2M88S7GDk5JARMJD7tWcYGYYtJXLi3 HswWEljEKHF6hk0XIxeQvZ5JovXJRFaQBJuAgcSjhe/YQWwRAQ2JKV2PgWwODmaBAIm732xA wsICPhK/l88Dm8MioCqxZNtcsFZeAU+J68f2skLsUpLY0HuUCcTmFPCSmPJ+NtReT4kzC2cz T2DkXcDIsIpRNLUguaA4KT3XSK84Mbe4NC9dLzk/dxMj2N/PpHcwrmqwOMQowMGoxMP7YNM/ fyHWxLLiytxDjBIczEoivP25QCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8Jt5f/YUE0hNLUrNT UwtSi2CyTBycUg2MbdcdWxzvWBa12ZWdMsptLCtNmvop40Su9uTzHMZveJ4IXBWKUNjqm7Rm q8Q+g5cT9nm7MH4625R15nmis8WhvOtNBerlxeoTRUzv8J+PEFLI7WKw/n6c129X+SWxDWrf uk/PuqPv+6rpjK5qjvqKq1dOZKyTsjat/sM+p8r/5aEEnjQDT38lluKMREMt5qLiRAAluK8R 8wEAAA== X-TM-AS-MML: No X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, linux-samsung-soc@vger.kernel.org, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add clock instances for bus interface unit clock and card interface unit clock of the all four MSHC controller instances. Signed-off-by: Abhilash Kesavan Signed-off-by: Thomas Abraham --- arch/arm/mach-exynos/clock-exynos5.c | 45 ++++++++++++---------------------- 1 files changed, 16 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336..02038d8 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peris_ctrl, .ctrlbit = (1 << 19), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.0", + .name = "biu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.1", + .name = "biu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.2", + .name = "biu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.3", + .name = "biu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), }, { - .name = "dwmci", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 16), - }, { .name = "sata", .devname = "ahci", .enable = exynos5_clk_ip_fsys_ctrl, @@ -992,8 +987,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.0", + .name = "ciu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1003,8 +998,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.1", + .name = "ciu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1014,8 +1009,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.2", + .name = "ciu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1025,8 +1020,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.3", + .name = "ciu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1037,14 +1032,6 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { - .name = "sclk_dwmci", - .parent = &exynos5_clk_dout_mmc4.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - }, { - .clk = { .name = "sclk_fimd", .devname = "s3cfb.1", .enable = exynos5_clksrc_mask_disp1_0_ctrl,