From patchwork Fri Jul 13 16:37:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 1204051 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 610303FC8E for ; Tue, 17 Jul 2012 09:03:06 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Sr3bm-0004uT-CS; Tue, 17 Jul 2012 08:58:18 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Spisg-0000nB-Hk for linux-arm-kernel@lists.infradead.org; Fri, 13 Jul 2012 16:38:25 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6DGc40q030892; Fri, 13 Jul 2012 11:38:04 -0500 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6DGc4S3004055; Fri, 13 Jul 2012 11:38:04 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Fri, 13 Jul 2012 11:38:04 -0500 Received: from localhost.localdomain (h64-15.vpn.ti.com [172.24.64.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6DGbxqd001357; Fri, 13 Jul 2012 11:38:03 -0500 From: Tero Kristo To: , , Subject: [RFC 2/6] ARM: OMAP3: clock data: prevent IVA2 DPLL low power stop mode Date: Fri, 13 Jul 2012 19:37:35 +0300 Message-ID: <1342197459-7920-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1342197459-7920-1-git-send-email-t-kristo@ti.com> References: <1342197459-7920-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-Mailman-Approved-At: Tue, 17 Jul 2012 04:58:13 -0400 Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org If IVA2 DPLL is in low power stop mode, this will prevent IVA2 powerdomain sleep transition. Typically the DPLL is in locked autoidle mode, which will allow sleep. With the wrong config, the DPLL will end up in the wrong mode if IVA2 clock is first enabled, then disabled by SW. This happens for example once IVA2 hwmod reset sequence is implemented properly within hwmod preprogram hook, as the IVA2 clock must be enabled during this. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock3xxx_data.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 1efdec2..3b7e9c8 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -353,8 +353,7 @@ static struct dpll_data dpll2_dd = { .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | - (1 << DPLL_LOW_POWER_BYPASS), + .modes = (1 << DPLL_LOCKED) | (1 << DPLL_LOW_POWER_BYPASS), .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,