From patchwork Sun Jul 15 14:49:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 1198981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 0FC393FD4F for ; Sun, 15 Jul 2012 14:54:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SqQA4-0003FV-DH; Sun, 15 Jul 2012 14:51:05 +0000 Received: from mail-wi0-f171.google.com ([209.85.212.171]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SqQ9e-0003E2-46 for linux-arm-kernel@lists.infradead.org; Sun, 15 Jul 2012 14:50:44 +0000 Received: by wibhq4 with SMTP id hq4so1534041wib.0 for ; Sun, 15 Jul 2012 07:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=BTZozM5OmOseG4FNROpvjNPrtBEqjgUPZ22GAMklgjo=; b=OF8dPf2inJBuQp+R3gyvW0gDKNcbWGex+hPp6bEFe1IOfMlUXRthFRPk2noDbcvaYw b0KDpJMmRdiYoPqGja+hDSoI9d2bvRtNDvfEVDXT+gIs+WJHLcVpKFD0Yq3aHzS7VfTV fuADpTSiIKg+9N/u3DxQm2kMNk13czVNfJJV0I98BqGZzG80Bnr1jtOUI8YNil4tZAon 4LKvsQ4DWOW0bTtWfEPSP2TBcE5dX7Hdn0NQ4eho1M+FQAzTTPRnJB6Bjztaup8cz0Dh EDSA2+ivQ2I2PHg/TF//XaNY5EHorvzUlyGARPkQhFSg5h8+kCf3ywBitPRrAb7eWQ1I QCnA== Received: by 10.180.99.232 with SMTP id et8mr11479823wib.11.1342363771459; Sun, 15 Jul 2012 07:49:31 -0700 (PDT) Received: from localhost.localdomain ([78.251.81.37]) by mx.google.com with ESMTPS id t7sm23788594wix.6.2012.07.15.07.49.29 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Jul 2012 07:49:30 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/8] ARM: MCS814x: add Device Tree based MCS8140 board support Date: Sun, 15 Jul 2012 16:49:08 +0200 Message-Id: <1342363754-30808-3-git-send-email-florian@openwrt.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1342363754-30808-1-git-send-email-florian@openwrt.org> References: <1342363754-30808-1-git-send-email-florian@openwrt.org> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (f.fainelli[at]gmail.com) -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.171 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: olof@lixom.net, devicetree-discuss@lists.ozlabs.org, Florian Fainelli , arnd@arndb.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds a generic MCS8140-based device tree registration board along with the corresponding mcs8140.dtsi file. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/mcs8140.dtsi | 207 ++++++++++++++++++++++++++++++ arch/arm/mach-mcs814x/board-mcs8140-dt.c | 44 +++++++ 2 files changed, 251 insertions(+) create mode 100644 arch/arm/boot/dts/mcs8140.dtsi create mode 100644 arch/arm/mach-mcs814x/board-mcs8140-dt.c diff --git a/arch/arm/boot/dts/mcs8140.dtsi b/arch/arm/boot/dts/mcs8140.dtsi new file mode 100644 index 0000000..7888026 --- /dev/null +++ b/arch/arm/boot/dts/mcs8140.dtsi @@ -0,0 +1,207 @@ +/* + * mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Moschip MCS8140 family SoC"; + compatible = "moschip,mcs8140"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uart0; + eth0 = ð0; + }; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vci { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + eth0: ethernet@40084000 { + compatible = "moschip,nuport-mac"; + reg = <0x40084000 0xd8 // mac + 0x40080000 0x58>; // dma channels + interrupts = <4 5 29>; /* tx, rx, link */ + nuport-mac,buffer-shifting; + nuport-mac,link-activity = <0>; + }; + + tso@40088000 { + reg = <0x40088000 0x1c>; + interrupts = <7>; + }; + + i2s@4008c000 { + compatible = "moschip,mcs814x-i2s"; + reg = <0x4008c000 0x18>; + interrupts = <8>; + }; + + ipsec@40094000 { + compatible = "moschip,mcs814x-ipsec"; + reg = <0x40094000 0x1d8>; + interrupts = <16>; + }; + + rng@4009c000 { + compatible = "moschip,mcs814x-rng"; + reg = <0x4009c000 0x8>; + }; + + memc@400a8000 { + reg = <0x400a8000 0x58>; + }; + + list-proc@400ac0c0 { + reg = <0x400ac0c0 0x38>; + interrupts = <19 27>; // done, error + }; + + pci@400b0000 { + compatible = "moschip,mcs814x-pci"; + reg = <0x400b0000 0x44 // PCI master + 0x400d8000 0xe4>; // EEPROM emulator + interrupts = <25>; // abort interrupt + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0 0x80000000 0x80000000 0 0x04000000 // IO + 0x42000000 0 0x90000000 0x90000000 0 0x20000000 // non-prefetch + 0x02000000 0 0xb0000000 0xb0000000 0 0x10000000>; // prefecth + + #interrupt-cells = <1>; + interrupt-map-mask = <>; + interrupt-map = <0 0 0 1 &intc 22 0 + 0 0 0 2 &intc 23 0 + 0 0 0 3 &intc 24 0 + 0 0 0 4 &intc 26 0>; + }; + + gpio: gpio@400d0000 { + compatible = "moschip,mcs814x-gpio"; + reg = <0x400d0000 0x670>; + interrupts = <10>; + #gpio-cells = <2>; + gpio-controller; + num-gpios = <20>; + }; + + eepio: gpio@400d4000 { + compatible = "moschip,mcs814x-gpio"; + reg = <0x400d4000 0x470>; + #gpio-cells = <2>; + gpio-controller; + num-gpios = <4>; + }; + + uart0: serial@400dc000 { + compatible = "ns16550"; + reg = <0x400dc000 0x20>; + clock-frequency = <50000000>; + reg-shift = <2>; + interrupts = <21>; + status = "okay"; + }; + + intc: interrupt-controller@400e4000 { + #interrupt-cells = <1>; + compatible = "moschip,mcs814x-intc"; + interrupt-controller; + interrupt-parent; + reg = <0x400e4000 0x48>; + }; + + m2m@400e8000 { + reg = <0x400e8000 0x24>; + interrupts = <17>; + }; + + eth-filters@400ec000 { + reg = <0x400ec000 0x80>; + }; + + timer: timer@400f800c { + compatible = "moschip,mcs814x-timer"; + interrupts = <0>; + reg = <0x400f800c 0x8>; + }; + + watchdog@400f8014 { + compatible = "moschip,mcs814x-wdt"; + reg = <0x400f8014 0x8>; + }; + + adc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + // 8 64MB chip-selects + ranges = <0 0 0x00000000 0x4000000 // sdram + 1 0 0x04000000 0x4000000 // sdram + 2 0 0x08000000 0x4000000 // reserved + 3 0 0x0c000000 0x4000000 // flash/localbus + 4 0 0x10000000 0x4000000 // flash/localbus + 5 0 0x14000000 0x4000000 // flash/localbus + 6 0 0x18000000 0x4000000 // flash/localbus + 7 0 0x1c000000 0x4000000>; // flash/localbus + + sdram: memory@0,0 { + reg = <0 0 0>; + }; + + nor: flash@7,0 { + reg = <7 0 0x4000000>; + compatible = "cfi-flash"; + bank-width = <1>; // 8-bit external flash + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + usb0: ehci@400fc000 { + compatible = "moschip,mcs814x-ehci", "usb-ehci"; + reg = <0x400fc000 0x74>; + interrupts = <2>; + }; + + usb1: ohci@400fd000 { + compatible = "moschip,mcs814x-ohci", "ohci-le"; + reg = <0x400fd000 0x74>; + interrupts = <11>; + }; + + usb2: ohci@400fe000 { + compatible = "moschip,mcs814x-ohci", "ohci-le"; + reg = <0x400fe000 0x74>; + interrupts = <12>; + }; + + usb3: otg@400ff000 { + compatible = "moschip,msc814x-otg", "usb-otg"; + reg = <0x400ff000 0x1000>; + interrupts = <13>; + }; + }; + + }; +}; diff --git a/arch/arm/mach-mcs814x/board-mcs8140-dt.c b/arch/arm/mach-mcs814x/board-mcs8140-dt.c new file mode 100644 index 0000000..5d13283 --- /dev/null +++ b/arch/arm/mach-mcs814x/board-mcs8140-dt.c @@ -0,0 +1,44 @@ +/* + * Setup code for Moschip MCS8140-based board using Device Tree + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2. + */ +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#include +#include +#include +#include +#include + +static void __init mcs814x_dt_device_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + mcs814x_init_machine(); +} + +static const char *mcs8140_dt_board_compat[] __initdata = { + "moschip,mcs8140", + NULL, /* sentinel */ +}; + +DT_MACHINE_START(mcs8140_dt, "Moschip MCS8140 board") + /* Maintainer: Florian Fainelli */ + .timer = &mcs814x_timer, + .map_io = mcs814x_map_io, + .init_early = mcs814x_clk_init, + .init_irq = mcs814x_of_irq_init, + .init_machine = mcs814x_dt_device_init, + .restart = mcs814x_restart, + .dt_compat = mcs8140_dt_board_compat, +MACHINE_END +