From patchwork Mon Jul 16 12:09:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1200691 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 0520A3FC33 for ; Mon, 16 Jul 2012 12:13:58 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Sqk8g-0002sz-67; Mon, 16 Jul 2012 12:10:58 +0000 Received: from mail-out.m-online.net ([212.18.0.10]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Sqk80-0002qE-FZ for linux-arm-kernel@lists.infradead.org; Mon, 16 Jul 2012 12:10:23 +0000 Received: from frontend4.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3WbNlH2Cj9z3hhds; Mon, 16 Jul 2012 14:11:39 +0200 (CEST) Received: from mashiro.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3WbNjc3mR6zbbfN; Mon, 16 Jul 2012 14:10:12 +0200 (CEST) From: Marek Vasut To: spi-devel-general@lists.sourceforge.net Subject: [PATCH 03/10] mmc: spi: Add necessary bits into mxs-spi.h Date: Mon, 16 Jul 2012 14:09:50 +0200 Message-Id: <1342440597-8395-4-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1342440597-8395-1-git-send-email-marex@denx.de> References: <1342440597-8395-1-git-send-email-marex@denx.de> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.18.0.10 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Marek Vasut , Fabio Estevam , Shawn Guo , Wolfgang Denk , Detlev Zundel , Stefano Babic , attila@kinali.ch, Grant Likely , Rob Herring , Chris Ball , Dong Aisheng , Linux ARM kernel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add missing register bits and registers into mxs-spi.h . These will be used by the SPI driver. Based on previous attempt by: Fabio Estevam Signed-off-by: Fabio Estevam Signed-off-by: Marek Vasut Cc: Chris Ball Cc: Detlev Zundel CC: Dong Aisheng Cc: Grant Likely Cc: Linux ARM kernel Cc: Rob Herring CC: Shawn Guo Cc: Stefano Babic Cc: Wolfgang Denk --- include/linux/spi/mxs-spi.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h index c08aef5..b0a0335 100644 --- a/include/linux/spi/mxs-spi.h +++ b/include/linux/spi/mxs-spi.h @@ -30,12 +30,14 @@ #define HW_SSP_CTRL0 0x000 #define BM_SSP_CTRL0_RUN (1 << 29) #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) +#define BM_SSP_CTRL0_LOCK_CS (1 << 27) #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) #define BM_SSP_CTRL0_READ (1 << 25) #define BM_SSP_CTRL0_DATA_XFER (1 << 24) #define BP_SSP_CTRL0_BUS_WIDTH 22 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20) #define BM_SSP_CTRL0_LONG_RESP (1 << 19) #define BM_SSP_CTRL0_GET_RESP (1 << 17) #define BM_SSP_CTRL0_ENABLE (1 << 16) @@ -64,8 +66,12 @@ #define BM_SSP_TIMING_TIMEOUT (0xffff << 16) #define BP_SSP_TIMING_CLOCK_DIVIDE 8 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) #define BP_SSP_TIMING_CLOCK_RATE 0 #define BM_SSP_TIMING_CLOCK_RATE 0xff +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080) #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) @@ -84,11 +90,26 @@ #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) +#define BM_SSP_CTRL1_PHASE (1 << 10) #define BM_SSP_CTRL1_POLARITY (1 << 9) #define BP_SSP_CTRL1_WORD_LENGTH 4 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF #define BP_SSP_CTRL1_SSP_MODE 0 #define BM_SSP_CTRL1_SSP_MODE 0xf +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 + +#define HW_SSP_DATA 0x090 + #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0) #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0) #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0) @@ -96,6 +117,7 @@ #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100) #define BM_SSP_STATUS_CARD_DETECT (1 << 28) #define BM_SSP_STATUS_SDIO_IRQ (1 << 17) +#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5) #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)