From patchwork Wed Jul 18 05:57:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leela Krishna Amudala X-Patchwork-Id: 1208591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 76BF23FCFC for ; Wed, 18 Jul 2012 05:51:39 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SrN4i-0004PQ-LJ; Wed, 18 Jul 2012 05:45:28 +0000 Received: from mailout1.samsung.com ([203.254.224.24]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SrN2S-000485-HT for linux-arm-kernel@lists.infradead.org; Wed, 18 Jul 2012 05:43:24 +0000 Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7C00CT5D7IHOP0@mailout1.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 18 Jul 2012 14:43:04 +0900 (KST) X-AuditID: cbfee61b-b7f566d000005c8a-a4-50064ce63e58 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 9E.EE.23690.6EC46005; Wed, 18 Jul 2012 14:43:03 +0900 (KST) Received: from localhost.localdomain ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7C000CUD7GD990@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 18 Jul 2012 14:43:02 +0900 (KST) From: Leela Krishna Amudala To: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 1/7] ARM: SAMSUNG: add additional registers and SFR definitions for writeback Date: Wed, 18 Jul 2012 11:27:27 +0530 Message-id: <1342591053-7092-2-git-send-email-l.krishna@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1342591053-7092-1-git-send-email-l.krishna@samsung.com> References: <1342591053-7092-1-git-send-email-l.krishna@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIJMWRmVeSWpSXmKPExsVy+t9jAd3nPmwBBguWsVhsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6MFQfPMhdcNay4eXkZWwPjWrUuRk4OCQETiaWfPjJD2GISF+6t ZwOxhQQWMUq83GXUxcgFZG9gknj64xVYgk3AWOL+3M1MXYwcHCICvhLfGvxBapgF1jBKrN08 D2yQsECSxMSbV8HqWQRUJf7/Pgdm8wq4SJxb/JcRYpmCROuyQ+wgNqeAq0TjqjNMEItdJPYu 3cg8gZF3ASPDKkbR1ILkguKk9FwjveLE3OLSvHS95PzcTYxgjz+T3sG4qsHiEKMAB6MSD2+D O1uAEGtiWXFl7iFGCQ5mJRFeweesAUK8KYmVValF+fFFpTmpxYcYpTlYlMR5Tby/+gsJpCeW pGanphakFsFkmTg4pRoYm1+rTbnYsqQgsZ65cWrroddr54Ypn5F0NDW81672yHHLNveZLgmL b0r3N5eumnLwZOuq+8u2ed7zlLVdKTCD4U92xUH532Gyf75/Wnbxwgn1Ut2XnPpr1yzrqnv2 L87yh8ycQ2nbd751c9+os4XD/Mb3SReefMvpzAi6qTT/8+9tydxpx5IPKCqxFGckGmoxFxUn AgDsnx3D9AEAAA== X-TM-AS-MML: No X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.24 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, jg1.han@samsung.com, joshi@samsung.com, grant.likely@secretlab.ca, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, olofj@google.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch updates the register address offsets and adds SFR definitions for writeback for Samsung's V8 display controller. Signed-off-by: Leela Krishna Amudala --- arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 10 ++++ arch/arm/plat-samsung/include/plat/regs-fb.h | 51 +++++++++++++++++++++++ drivers/video/Kconfig | 6 +++ 3 files changed, 67 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 4c3647f..1639c17 100644 --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h @@ -30,9 +30,16 @@ #define VIDCON1_FSTATUS_EVEN (1 << 15) /* Video timing controls */ +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDTCON0 (0x20010) +#define VIDTCON1 (0x20014) +#define VIDTCON3 (0x2001C) +#else #define VIDTCON0 (0x10) #define VIDTCON1 (0x14) #define VIDTCON2 (0x18) +#define VIDTCON3 (0x1C) +#endif /* Window position controls */ @@ -43,9 +50,12 @@ #define VIDOSD_BASE (0x40) #define VIDINTCON0 (0x130) +#define VIDINTCON1 (0x134) /* WINCONx */ +#define WINCONx_CSC_CON_EQ709 (1 << 28) +#define WINCONx_CSC_CON_EQ601 (0 << 28) #define WINCONx_CSCWIDTH_MASK (0x3 << 26) #define WINCONx_CSCWIDTH_SHIFT (26) #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h index 9a78012..6d2ee16 100644 --- a/arch/arm/plat-samsung/include/plat/regs-fb.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h @@ -32,12 +32,28 @@ #define VIDCON0 (0x00) #define VIDCON0_INTERLACE (1 << 29) + +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDOUT_CON (0x20000) +#define VIDOUT_CON_VIDOUT_UP_MASK (0x1 << 16) +#define VIDOUT_CON_VIDOUT_UP_SHIFT (16) +#define VIDOUT_CON_VIDOUT_UP_ALWAYS (0x0 << 16) +#define VIDOUT_CON_VIDOUT_UP_START_FRAME (0x1 << 16) +#define VIDOUT_CON_VIDOUT_F_MASK (0x7 << 8) +#define VIDOUT_CON_VIDOUT_F_SHIFT (8) +#define VIDOUT_CON_VIDOUT_F_RGB (0x0 << 8) +#define VIDOUT_CON_VIDOUT_F_I80_LDI0 (0x2 << 8) +#define VIDOUT_CON_VIDOUT_F_I80_LDI1 (0x3 << 8) +#define VIDOUT_CON_VIDOUT_F_WB (0x4 << 8) +#endif + #define VIDCON0_VIDOUT_MASK (0x3 << 26) #define VIDCON0_VIDOUT_SHIFT (26) #define VIDCON0_VIDOUT_RGB (0x0 << 26) #define VIDCON0_VIDOUT_TV (0x1 << 26) #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) +#define VIDCON0_VIDOUT_WB (0x4 << 26) #define VIDCON0_L1_DATA_MASK (0x7 << 23) #define VIDCON0_L1_DATA_SHIFT (23) @@ -81,7 +97,13 @@ #define VIDCON0_ENVID (1 << 1) #define VIDCON0_ENVID_F (1 << 0) +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDOUT_CON (0x20000) +#define VIDCON1 (0x20004) +#else #define VIDCON1 (0x04) +#endif + #define VIDCON1_LINECNT_MASK (0x7ff << 16) #define VIDCON1_LINECNT_SHIFT (16) #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) @@ -111,6 +133,14 @@ #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) +#define VIDCON2_TVFMTSEL1_SHIFT (12) +#define VIDCON2_TVFMTSEL_SW (1 << 14) +#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12) + +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) #define VIDCON2_ORGYCbCr (1 << 8) #define VIDCON2_YUVORDCrCb (1 << 7) @@ -165,8 +195,15 @@ #define VIDTCON1_HSPW_SHIFT (0) #define VIDTCON1_HSPW_LIMIT (0xff) #define VIDTCON1_HSPW(_x) ((_x) << 0) +#define VIDCON1_VCLK_MASK (0x3 << 9) +#define VIDCON1_VCLK_HOLD (0x0 << 9) +#define VIDCON1_VCLK_RUN (0x1 << 9) +#ifdef CONFIG_FB_EXYNOS_FIMD_V8 +#define VIDTCON2 (0x20018) +#else #define VIDTCON2 (0x18) +#endif #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT (11) @@ -186,6 +223,9 @@ #define WINCONx_BYTSWP (1 << 17) #define WINCONx_HAWSWP (1 << 16) #define WINCONx_WSWP (1 << 15) +#define WINCONx_ENLOCAL_MASK (0xf << 15) +#define WINCONx_INRGB_RGB (0 << 13) +#define WINCONx_INRGB_YCBCR (1 << 13) #define WINCONx_BURSTLEN_MASK (0x3 << 9) #define WINCONx_BURSTLEN_SHIFT (9) #define WINCONx_BURSTLEN_16WORD (0x0 << 9) @@ -205,6 +245,7 @@ #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) #define WINCON1_BLD_PIX (1 << 6) +#define WINCON1_BLD_PLANE (0 << 6) #define WINCON1_ALPHA_SEL (1 << 1) #define WINCON1_BPPMODE_MASK (0xf << 2) @@ -395,9 +436,19 @@ #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) +/* Clock gate mode control */ +#define REG_CLKGATE_MODE (0x1b0) +#define REG_CLKGATE_MODE_AUTO_CLOCK_GATE (0 << 0) +#define REG_CLKGATE_MODE_NON_CLOCK_GATE (1 << 0) + /* Blending equation control */ #define BLENDCON (0x260) #define BLENDCON_NEW_MASK (1 << 0) #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) +/* Window alpha control */ +#define VIDW0ALPHA0 (0x200) +#define VIDW0ALPHA1 (0x204) +#define DPCLKCON (0x27c) +#define DPCLKCON_ENABLE (1 << 1) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 0217f74..f81bf55 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2053,6 +2053,12 @@ config FB_S3C Currently the support is only for the S3C6400 and S3C6410 SoCs. +config FB_EXYNOS_FIMD_V8 + bool "register extensions for FIMD version 8" + depends on ARCH_EXYNOS5 + ---help--- + This uses register extensions for FIMD version 8 + config FB_S3C_DEBUG_REGWRITE bool "Debug register writes" depends on FB_S3C