From patchwork Tue Jul 31 06:13:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Xie X-Patchwork-Id: 1258091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 58F6A3FC1A for ; Tue, 31 Jul 2012 06:31:56 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Sw5uN-0002ER-0g; Tue, 31 Jul 2012 06:26:19 +0000 Received: from na3sys009aog135.obsmtp.com ([74.125.149.84]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1Sw5r7-0001sD-WD for linux-arm-kernel@lists.infradead.org; Tue, 31 Jul 2012 06:22:59 +0000 Received: from MSI-MTA.marvell.com ([65.219.4.132]) (using TLSv1) by na3sys009aob135.postini.com ([74.125.148.12]) with SMTP ID DSNKUBd5sBfHD+d8yWucdYHh1dxL7pSQ4ThC@postini.com; Mon, 30 Jul 2012 23:22:56 PDT Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 30 Jul 2012 23:13:08 -0700 Received: from localhost (unknown [10.38.36.110]) by maili.marvell.com (Postfix) with ESMTP id 6314B4E50D; Mon, 30 Jul 2012 23:13:08 -0700 (PDT) From: Chao Xie To: haojian.zhuang@gmail.com, linux-arm-kernel@lists.infradead.org, chao.xie@marvell.com Subject: [PATCH 5/7] ARM: cache: add extra feature enable for tauros2 Date: Tue, 31 Jul 2012 14:13:12 +0800 Message-Id: <1343715194-25900-5-git-send-email-xiechao.mail@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1343715194-25900-1-git-send-email-xiechao.mail@gmail.com> References: <1343715194-25900-1-git-send-email-xiechao.mail@gmail.com> X-OriginalArrivalTime: 31 Jul 2012 06:13:08.0753 (UTC) FILETIME=[8E4B1810:01CD6EE3] X-Spam-Note: CRM114 invocation failed X-Spam-Note: SpamAssassin invocation failed Cc: Chao Xie X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Chao Xie The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie --- arch/arm/include/asm/hardware/cache-tauros2.h | 5 ++- arch/arm/mm/cache-tauros2.c | 44 +++++++++++++++--------- 2 files changed, 31 insertions(+), 18 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h index 538f17c..295e2e4 100644 --- a/arch/arm/include/asm/hardware/cache-tauros2.h +++ b/arch/arm/include/asm/hardware/cache-tauros2.h @@ -8,4 +8,7 @@ * warranty of any kind, whether express or implied. */ -extern void __init tauros2_init(void); +#define CACHE_TAUROS2_PREFETCH_ON (1 << 0) +#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + +extern void __init tauros2_init(unsigned int features); diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 4b787bb..e9f054f 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -145,21 +145,6 @@ static inline void __init write_extra_features(u32 u) __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); } -static void __init disable_l2_prefetch(void) -{ - u32 u; - - /* - * Read the CPU Extra Features register and verify that the - * Disable L2 Prefetch bit is set. - */ - u = read_extra_features(); - if (!(u & 0x01000000)) { - printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); - write_extra_features(u | 0x01000000); - } -} - static inline int __init cpuid_scheme(void) { return !!((processor_id & 0x000f0000) == 0x000f0000); @@ -188,11 +173,36 @@ static inline void __init write_actlr(u32 actlr) __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); } -void __init tauros2_init(void) +static void enable_extra_feature(unsigned int features) +{ + u32 u; + + u = read_extra_features(); + + if (features & CACHE_TAUROS2_PREFETCH_ON) + u &= ~0x01000000; + else + u |= 0x01000000; + printk(KERN_INFO "Tauros2: %s L2 prefetch.\n", + (features & CACHE_TAUROS2_PREFETCH_ON) + ? "Enabling" : "Disabling"); + + if (features & CACHE_TAUROS2_LINEFILL_BURST8) + u |= 0x00100000; + else + u &= ~0x00100000; + printk(KERN_INFO "Tauros2: %s line fill burt8.\n", + (features & CACHE_TAUROS2_LINEFILL_BURST8) + ? "Enabling" : "Disabling"); + + write_extra_features(u); +} + +void __init tauros2_init(unsigned int features) { char *mode = NULL; - disable_l2_prefetch(); + enable_extra_feature(features); #ifdef CONFIG_CPU_32v5 if ((processor_id & 0xff0f0000) == 0x56050000) {