From patchwork Tue Jul 31 23:04:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 1262331 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 825C13FC71 for ; Tue, 31 Jul 2012 23:08:32 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SwLVg-0005Te-HZ; Tue, 31 Jul 2012 23:05:52 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SwLVL-0005PK-8u for linux-arm-kernel@lists.infradead.org; Tue, 31 Jul 2012 23:05:33 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6VN5Kjk029028; Tue, 31 Jul 2012 18:05:20 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6VN5K5S032732; Tue, 31 Jul 2012 18:05:20 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Tue, 31 Jul 2012 18:05:20 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6VN5JpG012372; Tue, 31 Jul 2012 18:05:20 -0500 Received: from a0875269 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1SwLV9-0007Ok-PF; Tue, 31 Jul 2012 19:05:19 -0400 From: Cyril Chemparathy To: , Subject: [PATCH 09/22] ARM: LPAE: use 64-bit pgd physical address in switch_mm() Date: Tue, 31 Jul 2012 19:04:45 -0400 Message-ID: <1343775898-28345-10-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343775898-28345-1-git-send-email-cyril@ti.com> References: <1343775898-28345-1-git-send-email-cyril@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux@arm.linux.org.uk, arnd@arndb.de, nico@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, Vitaly Andrianov , Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch modifies the switch_mm() processor functions to use 64-bit addresses. We use u64 instead of phys_addr_t, in order to avoid having config dependent register usage when calling into switch_mm assembly code. The changes in this patch are primarily adjustments for registers used for arguments to switch_mm. The few processor definitions that did use the second argument have been modified accordingly. Arguments and calling conventions aside, this patch should be a no-op on v6 and non-LPAE v7 processors. On LPAE systems, we now honor the upper 32-bits of the physical address that is being passed in. Signed-off-by: Cyril Chemparathy Signed-off-by: Vitaly Andrianov --- arch/arm/include/asm/proc-fns.h | 4 ++-- arch/arm/mm/proc-v6.S | 2 +- arch/arm/mm/proc-v7-2level.S | 2 +- arch/arm/mm/proc-v7-3level.S | 5 +++-- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index f3628fb..fa6554e 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -60,7 +60,7 @@ extern struct processor { /* * Set the page table */ - void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); + void (*switch_mm)(u64 pgd_phys, struct mm_struct *mm); /* * Set a possibly extended PTE. Non-extended PTEs should * ignore 'ext'. @@ -82,7 +82,7 @@ extern void cpu_proc_init(void); extern void cpu_proc_fin(void); extern int cpu_do_idle(void); extern void cpu_dcache_clean_area(void *, int); -extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +extern void cpu_do_switch_mm(u64 pgd_phys, struct mm_struct *mm); #ifdef CONFIG_ARM_LPAE extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte); #else diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 5900cd5..566c658 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -100,8 +100,8 @@ ENTRY(cpu_v6_dcache_clean_area) */ ENTRY(cpu_v6_switch_mm) #ifdef CONFIG_MMU + ldr r1, [r2, #MM_CONTEXT_ID] @ get mm->context.id mov r2, #0 - ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 42ac069..3397803 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -39,8 +39,8 @@ */ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU + ldr r1, [r2, #MM_CONTEXT_ID] @ get mm->context.id mov r2, #0 - ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 8de0f1d..0001581 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -47,9 +47,10 @@ */ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU - ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id - and r3, r1, #0xff + ldr r2, [r2, #MM_CONTEXT_ID] @ get mm->context.id + and r3, r2, #0xff mov r3, r3, lsl #(48 - 32) @ ASID + orr r3, r3, r1 @ upper 32-bits of pgd phys mcrr p15, 0, r0, r3, c2 @ set TTB 0 isb #endif