From patchwork Tue Jul 31 23:04:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 1262401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id CFDD53FC71 for ; Tue, 31 Jul 2012 23:09:18 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SwLXC-0005yL-MR; Tue, 31 Jul 2012 23:07:27 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SwLVU-0005P9-1e for linux-arm-kernel@lists.infradead.org; Tue, 31 Jul 2012 23:05:48 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6VN5Kb3015641; Tue, 31 Jul 2012 18:05:20 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6VN5KMv032761; Tue, 31 Jul 2012 18:05:20 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Tue, 31 Jul 2012 18:05:20 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6VN5K3M012387; Tue, 31 Jul 2012 18:05:20 -0500 Received: from a0875269 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1SwLVA-0007Ow-9C; Tue, 31 Jul 2012 19:05:20 -0400 From: Cyril Chemparathy To: , Subject: [PATCH 13/22] ARM: LPAE: allow proc override of TTB setup Date: Tue, 31 Jul 2012 19:04:49 -0400 Message-ID: <1343775898-28345-14-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343775898-28345-1-git-send-email-cyril@ti.com> References: <1343775898-28345-1-git-send-email-cyril@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.94.94.41 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux@arm.linux.org.uk, arnd@arndb.de, nico@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, Vitaly Andrianov , Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch allows ARM processor setup functions (*_setup in proc-*.S) to indicate that the page table has already been programmed. This is done by setting r4 (page table pointer) to -1 before returning from the processor setup handler. This capability is particularly needed on LPAE systems, where the translation table base needs to be programmed differently with 64-bit control register operations. Further, a few of the processors (arm1026, mohawk, xsc3) were programming the TTB twice. This patch prevents the main head.S code from programming TTB the second time on these machines. Signed-off-by: Cyril Chemparathy Signed-off-by: Vitaly Andrianov --- arch/arm/kernel/head.S | 10 +++++----- arch/arm/mm/proc-arm1026.S | 1 + arch/arm/mm/proc-mohawk.S | 1 + arch/arm/mm/proc-v6.S | 2 ++ arch/arm/mm/proc-v7-2level.S | 3 ++- arch/arm/mm/proc-v7-3level.S | 1 + arch/arm/mm/proc-v7.S | 1 + arch/arm/mm/proc-xsc3.S | 1 + 8 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index fa820b3..7b1a3be 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -414,17 +414,17 @@ __enable_mmu: #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif -#ifdef CONFIG_ARM_LPAE - mov r5, #0 - mcrr p15, 0, r4, r5, c2 @ load TTBR0 -#else +#ifndef CONFIG_ARM_LPAE mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ domain_val(DOMAIN_IO, DOMAIN_CLIENT)) mcr p15, 0, r5, c3, c0, 0 @ load domain access register - mcr p15, 0, r4, c2, c0, 0 @ load page table pointer #endif + + @ has the processor setup already programmed the page table pointer? + adds r5, r4, #1 + mcrne p15, 0, r4, c2, c0, 0 @ load page table pointer b __turn_mmu_on ENDPROC(__enable_mmu) diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index fbc1d5f..c28070e 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -404,6 +404,7 @@ __arm1026_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 mcr p15, 0, r4, c2, c0 @ load page table pointer + mvn r4, #0 @ do not set page table pointer #endif #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mov r0, #4 @ explicitly disable writeback diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index fbb2124..a26303c 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -390,6 +390,7 @@ __mohawk_setup: mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs orr r4, r4, #0x18 @ cache the page table in L2 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer + mvn r4, #0 @ do not set page table pointer mov r0, #0 @ don't allow CP access mcr p15, 0, r0, c15, c1, 0 @ write CP access register diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 566c658..872156e 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -210,7 +210,9 @@ __v6_setup: ALT_UP(orr r4, r4, #TTB_FLAGS_UP) ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) ALT_UP(orr r8, r8, #TTB_FLAGS_UP) + mcr p15, 0, r4, c2, c0, 0 @ load TTB0 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 + mvn r4, #0 @ do not set page table pointer #endif /* CONFIG_MMU */ adr r5, v6_crval ldmia r5, {r5, r6} diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 3397803..cc78c0c 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -139,7 +139,7 @@ ENDPROC(cpu_v7_set_pte_ext) /* * Macro for setting up the TTBRx and TTBCR registers. - * - \ttb0 and \ttb1 updated with the corresponding flags. + * - \ttbr0 and \ttbr1 updated with the corresponding flags. */ .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp mcr p15, 0, \zero, c2, c0, 2 @ TTB control register @@ -147,6 +147,7 @@ ENDPROC(cpu_v7_set_pte_ext) ALT_UP(orr \ttbr0, \ttbr0, #TTB_FLAGS_UP) ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP) + mcr p15, 0, \ttbr0, c2, c0, 0 @ load TTB0 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1 .endm diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 3b1a745..5e3bed1 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -124,6 +124,7 @@ ENDPROC(cpu_v7_set_pte_ext) mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR addls \ttbr1, \ttbr1, #TTBR1_OFFSET mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 + mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 .endm __CPUINIT diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2e2b66..8850194 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -250,6 +250,7 @@ __v7_setup: #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup + mvn r4, #0 @ do not set page table pointer ldr r5, =PRRR @ PRRR ldr r6, =NMRR @ NMRR mcr p15, 0, r5, c10, c2, 0 @ write PRRR diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index b0d5786..db3836b 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -455,6 +455,7 @@ __xsc3_setup: mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs orr r4, r4, #0x18 @ cache the page table in L2 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer + mvn r4, #0 @ do not set page table pointer mov r0, #1 << 6 @ cp6 access for early sched_clock mcr p15, 0, r0, c15, c1, 0 @ write CP access register