From patchwork Tue Jul 31 23:04:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 1262561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id BEE11DF26F for ; Tue, 31 Jul 2012 23:14:50 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SwLcI-00018v-Su; Tue, 31 Jul 2012 23:12:43 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SwLVZ-0005T3-FU for linux-arm-kernel@lists.infradead.org; Tue, 31 Jul 2012 23:06:05 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6VN5JEZ015625; Tue, 31 Jul 2012 18:05:19 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6VN5JJY032716; Tue, 31 Jul 2012 18:05:19 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Tue, 31 Jul 2012 18:05:19 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6VN5Jsv012359; Tue, 31 Jul 2012 18:05:19 -0500 Received: from a0875269 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1SwLV9-0007OV-43; Tue, 31 Jul 2012 19:05:19 -0400 From: Cyril Chemparathy To: , Subject: [PATCH 04/22] ARM: LPAE: support 64-bit virt/phys patching Date: Tue, 31 Jul 2012 19:04:40 -0400 Message-ID: <1343775898-28345-5-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343775898-28345-1-git-send-email-cyril@ti.com> References: <1343775898-28345-1-git-send-email-cyril@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.94.94.41 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux@arm.linux.org.uk, arnd@arndb.de, nico@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds support for 64-bit physical addresses in virt_to_phys patching. This does not do real 64-bit add/sub, but instead patches in the upper 32-bits of the phys_offset directly into the output of virt_to_phys. In addition to adding 64-bit support, this patch also adds a set_phys_offset() helper that is needed on architectures that need to modify PHYS_OFFSET during initialization. Signed-off-by: Cyril Chemparathy --- arch/arm/include/asm/memory.h | 22 +++++++++++++++------- arch/arm/kernel/head.S | 6 ++++++ arch/arm/kernel/setup.c | 14 ++++++++++++++ 3 files changed, 35 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 4a0108f..110495c 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -153,23 +153,31 @@ #ifdef CONFIG_ARM_PATCH_PHYS_VIRT extern unsigned long __pv_phys_offset; -#define PHYS_OFFSET __pv_phys_offset - +extern unsigned long __pv_phys_offset_high; extern unsigned long __pv_offset; +extern void set_phys_offset(phys_addr_t po); + +#define PHYS_OFFSET __virt_to_phys(PAGE_OFFSET) + static inline phys_addr_t __virt_to_phys(unsigned long x) { - unsigned long t; - early_patch_imm8(x, t, "add", __pv_offset); - return t; + unsigned long tlo, thi = 0; + + early_patch_imm8(x, tlo, "add", __pv_offset); + if (sizeof(phys_addr_t) > 4) + early_patch_imm8(0, thi, "add", __pv_phys_offset_high); + + return (u64)tlo | (u64)thi << 32; } static inline unsigned long __phys_to_virt(phys_addr_t x) { - unsigned long t; - early_patch_imm8(x, t, "sub", __pv_offset); + unsigned long t, xlo = x; + early_patch_imm8(xlo, t, "sub", __pv_offset); return t; } + #else #define __virt_to_phys(x) \ diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index d165896..fa820b3 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -532,6 +532,12 @@ __pv_phys_offset: .long 0 .size __pv_phys_offset, . - __pv_phys_offset + .globl __pv_phys_offset_high + .type __pv_phys_offset_high, %object +__pv_phys_offset_high: + .long 0 + .size __pv_phys_offset_high, . - __pv_phys_offset_high + .globl __pv_offset .type __pv_offset, %object __pv_offset: diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 15a7699..bba3fdc 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -67,6 +67,20 @@ #define MEM_SIZE (16*1024*1024) #endif +#ifdef CONFIG_ARM_PATCH_PHYS_VIRT +/* + * set_phys_offset() sets PHYS_OFFSET and pv_offset. + * Note: this is unsafe to use beyond setup_arch(). + */ +void __init set_phys_offset(phys_addr_t po) +{ + __pv_phys_offset = po; + __pv_phys_offset_high = (u64)po >> 32; + __pv_offset = po - PAGE_OFFSET; +} + +#endif + #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE) char fpe_type[8];