From patchwork Sat Aug 11 01:24:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 1307591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 0E11D3FC66 for ; Sat, 11 Aug 2012 01:35:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T00Y9-0003WD-QZ; Sat, 11 Aug 2012 01:31:35 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T00SW-0007yj-75 for linux-arm-kernel@lists.infradead.org; Sat, 11 Aug 2012 01:26:03 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q7B1PNKn015891; Fri, 10 Aug 2012 20:25:23 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q7B1PN1d010289; Fri, 10 Aug 2012 20:25:23 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Fri, 10 Aug 2012 20:25:23 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q7B1PNUv001378; Fri, 10 Aug 2012 20:25:23 -0500 Received: from a0875269 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1T00SB-00044j-2B; Fri, 10 Aug 2012 21:25:23 -0400 From: Cyril Chemparathy To: , Subject: [PATCH v2 05/22] ARM: LPAE: support 64-bit virt_to_phys patching Date: Fri, 10 Aug 2012 21:24:48 -0400 Message-ID: <1344648306-15619-6-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com> References: <1344648306-15619-1-git-send-email-cyril@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.41 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux@arm.linux.org.uk, arnd@arndb.de, nico@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, grant.likely@secretlab.ca, Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds support for 64-bit physical addresses in virt_to_phys() patching. This does not do real 64-bit add/sub, but instead patches in the upper 32-bits of the phys_offset directly into the output of virt_to_phys. There is no corresponding change on the phys_to_virt() side, because computations on the upper 32-bits would be discarded anyway. Signed-off-by: Cyril Chemparathy --- arch/arm/include/asm/memory.h | 22 ++++++++++++++++++---- arch/arm/kernel/head.S | 4 ++++ arch/arm/kernel/setup.c | 2 +- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 81e1714..dc5fbf3 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -154,14 +154,28 @@ #ifdef CONFIG_ARM_PATCH_PHYS_VIRT extern unsigned long __pv_offset; -extern unsigned long __pv_phys_offset; +extern phys_addr_t __pv_phys_offset; #define PHYS_OFFSET __virt_to_phys(PAGE_OFFSET) static inline phys_addr_t __virt_to_phys(unsigned long x) { - unsigned long t; - early_patch_imm8("add", t, x, __pv_offset, 0); - return t; + unsigned long tlo, thi; + + early_patch_imm8("add", tlo, x, __pv_offset, 0); + +#ifdef CONFIG_ARM_LPAE + /* + * On LPAE, we do not _need_ to do 64-bit arithmetic because the high + * order 32 bits are never changed by the phys-virt offset. We simply + * patch in the high order physical address bits instead. + */ +#ifdef __ARMEB__ + early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0); +#else + early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4); +#endif +#endif + return (u64)tlo | (u64)thi << 32; } static inline unsigned long __phys_to_virt(phys_addr_t x) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 69a3c09..61fb8df 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -530,7 +530,11 @@ ENDPROC(__fixup_pv_offsets) .align 1: .long . +#if defined(CONFIG_ARM_LPAE) && defined(__ARMEB__) + .long __pv_phys_offset + 4 +#else .long __pv_phys_offset +#endif .long __pv_offset .long PAGE_OFFSET #endif diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 59e0f57..edb4f42 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -159,7 +159,7 @@ DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data); * The initializers here prevent these from landing in the BSS section. */ unsigned long __pv_offset = 0xdeadbeef; -unsigned long __pv_phys_offset = 0xdeadbeef; +phys_addr_t __pv_phys_offset = 0xdeadbeef; EXPORT_SYMBOL(__pv_phys_offset); #endif