From patchwork Mon Aug 13 13:05:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 1312781 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id D7F45DF223 for ; Mon, 13 Aug 2012 13:10:55 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T0uML-0000tV-Ro; Mon, 13 Aug 2012 13:07:06 +0000 Received: from ch1ehsobe002.messaging.microsoft.com ([216.32.181.182] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T0uKM-0000B5-NC for linux-arm-kernel@lists.infradead.org; Mon, 13 Aug 2012 13:05:04 +0000 Received: from mail222-ch1-R.bigfish.com (10.43.68.227) by CH1EHSOBE002.bigfish.com (10.43.70.52) with Microsoft SMTP Server id 14.1.225.23; Mon, 13 Aug 2012 13:04:54 +0000 Received: from mail222-ch1 (localhost [127.0.0.1]) by mail222-ch1-R.bigfish.com (Postfix) with ESMTP id BF4D41C03A6; Mon, 13 Aug 2012 13:04:54 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zcb8kzzz1202hzz8275dhz2dh87h2a8h668h839hd24he5bhe96hf0ah107ah) X-FB-DOMAIN-IP-MATCH: fail Received: from mail222-ch1 (localhost.localdomain [127.0.0.1]) by mail222-ch1 (MessageSwitch) id 1344863092948806_27109; Mon, 13 Aug 2012 13:04:52 +0000 (UTC) Received: from CH1EHSMHS016.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.253]) by mail222-ch1.bigfish.com (Postfix) with ESMTP id DC174220097; Mon, 13 Aug 2012 13:04:52 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS016.bigfish.com (10.43.70.16) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 13 Aug 2012 13:04:52 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.2.298.5; Mon, 13 Aug 2012 08:04:51 -0500 Received: from S2101-09.ap.freescale.net ([10.192.185.246]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q7DD4cfL032376; Mon, 13 Aug 2012 06:04:50 -0700 From: Shawn Guo To: Subject: [PATCH 06/17] ARM: dts: imx6q-sabresd: add pinctrl settings Date: Mon, 13 Aug 2012 21:05:26 +0800 Message-ID: <1344863137-6112-7-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org> References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.181.182 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add pinctrl settings for existing devices in imx6q-sabresd.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabresd.dts | 25 ++++++++++++++++++++++++- arch/arm/boot/dts/imx6q.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 07509a1..e596c28c 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -22,28 +22,51 @@ }; soc { - aips-bus@02000000 { /* AIPS1 */ spba-bus@02000000 { uart1: serial@02020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; + + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ + 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ + 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ + 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ + >; + }; + }; + }; }; aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; status = "okay"; }; usdhc@02194000 { /* uSDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 23d680a..3b97212 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -602,6 +602,15 @@ }; }; + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ + 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ + >; + }; + }; + uart2 { pinctrl_uart2_1: uart2grp-1 { fsl,pins = < @@ -620,6 +629,23 @@ }; }; + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ + 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ + 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ + 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ + 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ + >; + }; + }; + usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { fsl,pins = <