From patchwork Sun Aug 19 20:00:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yan Burman X-Patchwork-Id: 1347141 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 383D7DFF0F for ; Mon, 20 Aug 2012 08:53:57 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T3Nhj-0007kv-Go; Mon, 20 Aug 2012 08:51:23 +0000 Received: from mail-we0-f177.google.com ([74.125.82.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T3Nhg-0007je-Ax for linux-arm-kernel@lists.infradead.org; Mon, 20 Aug 2012 08:51:21 +0000 Received: by weyr3 with SMTP id r3so4100875wey.36 for ; Mon, 20 Aug 2012 01:51:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=YgCpT/eTRk3YhIUgxgfcc0GQgo5xXqYiMeQGpnM5Q7E=; b=Y2gyFn5plrFiTgUd4o0bgDsQWn2OhKeGd360sHWAg6+fm9A9PibEagH738RHXU5X6A bsA8e4KasE01+qoUgp50Ong5/5q2NgpQVgVdPZE8IDcxDOCxSQpqBBLlA2qY0rv1cZZw /0wMWl7CztB9x2biM0w9DWpC7M1PBpNxXGRjf3H0u4H0S8xotBqyuwpA399AIUMcMxCL b+7AgcSXXpvHUFd5J6VldwhCCelkQYt5WIjXoiJs91SXsuIpAOI7mvzY/DqSVjIjng6s 8wsbGeHHf15T+uWd/wfu7aU1E66csKTmJT3L9V7b7Jzndc/dHN9gz4NGQ60wdNSK2MC7 yNIg== Received: by 10.180.105.130 with SMTP id gm2mr26099253wib.6.1345452670814; Mon, 20 Aug 2012 01:51:10 -0700 (PDT) Received: from [10.0.0.26] (IGLD-84-228-68-178.inter.net.il. [84.228.68.178]) by mx.google.com with ESMTPS id b7sm40093016wiz.9.2012.08.20.01.51.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 20 Aug 2012 01:51:10 -0700 (PDT) Subject: [PATCH v2] ARM: ep93xx: clockevent support From: Yan Burman To: linux-arm-kernel@lists.infradead.org, rmallon@gmail.com, hsweeten@visionengravers.com Date: Sun, 19 Aug 2012 23:00:44 +0300 Message-Id: <1345406444.20237.7.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.6.3 (2.6.3-2.fc5) X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.7 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (burman.yan[at]gmail.com) 1.0 DATE_IN_PAST_12_24 Date: is 12 to 24 hours before Received: date -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ARM: ep93xx: clockevent support I have ported to 3.6-rc2 and slightly modified a previous patch for clockevent support for the ep93xx. The porting mainly consists of sched_clock support + CLKSRC_MMIO usage. Tested on 9302 based board. Changes from v1: * Number of cosmetic style fixes * Use CLKSRC_MMIO From: Ahmed Ammar edge-techno.com> Signed-off-by: Yan Burman diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e91c7cd..b1d0b11 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -451,7 +451,8 @@ config ARCH_EP93XX select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_USES_GETTIMEOFFSET + select GENERIC_CLOCKEVENTS + select CLKSRC_MMIO select NEED_MACH_MEMORY_H help This enables support for the Cirrus EP93xx series of CPUs. diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 4afe52a..f59a849 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include #include #include @@ -43,6 +45,7 @@ #include #include +#include #include @@ -114,63 +117,114 @@ void __init ep93xx_map_io(void) #define EP93XX_TIMER4_CLOCK 983040 #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) -#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) - -static unsigned int last_jiffy_time; static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) { + struct clock_event_device *evt = dev_id; + /* Writing any value clears the timer interrupt */ __raw_writel(1, EP93XX_TIMER1_CLEAR); - - /* Recover lost jiffies */ - while ((signed long) - (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) - >= TIMER4_TICKS_PER_JIFFY) { - last_jiffy_time += TIMER4_TICKS_PER_JIFFY; - timer_tick(); - } + evt->event_handler(evt); return IRQ_HANDLED; } +static int ep93xx_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + u32 tmode = __raw_readl(EP93XX_TIMER1_CONTROL); + + /* stop timer */ + __raw_writel(tmode & ~EP93XX_TIMER123_CONTROL_ENABLE, + EP93XX_TIMER1_CONTROL); + /* program timer */ + __raw_writel(evt, EP93XX_TIMER1_LOAD); + /* start timer */ + __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, + EP93XX_TIMER1_CONTROL); + + return 0; +} + +static void ep93xx_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + u32 tmode = EP93XX_TIMER123_CONTROL_CLKSEL; + + /* Disable timer */ + __raw_writel(tmode, EP93XX_TIMER1_CONTROL); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Set timer period */ + __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); + tmode |= EP93XX_TIMER123_CONTROL_MODE; + /* fall through */ + + case CLOCK_EVT_MODE_ONESHOT: + tmode |= EP93XX_TIMER123_CONTROL_ENABLE; + __raw_writel(tmode, EP93XX_TIMER1_CONTROL); + break; + + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device ep93xx_clockevent = { + .name = "ep93xx-timer1", + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .set_mode = ep93xx_set_mode, + .set_next_event = ep93xx_set_next_event, +}; + static struct irqaction ep93xx_timer_irq = { .name = "ep93xx timer", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = ep93xx_timer_interrupt, + .dev_id = &ep93xx_clockevent, }; -static void __init ep93xx_timer_init(void) +static void __init ep93xx_clockevent_init(void) { - u32 tmode = EP93XX_TIMER123_CONTROL_MODE | - EP93XX_TIMER123_CONTROL_CLKSEL; + struct clock_event_device *evt = &ep93xx_clockevent; - /* Enable periodic HZ timer. */ - __raw_writel(tmode, EP93XX_TIMER1_CONTROL); - __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); - __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, - EP93XX_TIMER1_CONTROL); - - /* Enable lost jiffy timer. */ - __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, - EP93XX_TIMER4_VALUE_HIGH); + evt->mult = div_sc(EP93XX_TIMER123_CLOCK, NSEC_PER_SEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xfffffffe, evt); + evt->min_delta_ns = clockevent_delta2ns(0xf, evt); + evt->cpumask = cpumask_of(0); setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); + + clockevents_register_device(evt); } -static unsigned long ep93xx_gettimeoffset(void) +static void __init ep93xx_clocksource_init(void) { - int offset; + /* Reset time-stamp counter */ + __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, EP93XX_TIMER4_VALUE_HIGH); + + clocksource_mmio_init(EP93XX_TIMER4_VALUE_LOW, "ep93xx-timer4", + CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); +} - offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; +static u32 notrace ep93xx_sched_clock(void) +{ + return __raw_readl(EP93XX_TIMER4_VALUE_LOW); +} - /* Calculate (1000000 / 983040) * offset. */ - return offset + (53 * offset / 3072); +static void __init ep93xx_timer_init(void) +{ + ep93xx_clocksource_init(); + ep93xx_clockevent_init(); + setup_sched_clock(ep93xx_sched_clock, 32, CLOCK_TICK_RATE); } struct sys_timer ep93xx_timer = { .init = ep93xx_timer_init, - .offset = ep93xx_gettimeoffset, };