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[192.94.94.33]) by mx.google.com with ESMTPS id bp7sm22491641obc.12.2012.08.29.06.31.10 (version=SSLv3 cipher=OTHER); Wed, 29 Aug 2012 06:31:12 -0700 (PDT) From: Peter Ujfalusi To: Tony Lindgren Subject: [PATCH v2 4/8] ARM/dts: OMAP4: Add McBSP entries Date: Wed, 29 Aug 2012 16:31:03 +0300 Message-Id: <1346247067-9632-5-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.7.8.6 In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com> References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com> X-Gm-Message-State: ALoCoQnI6uD1fncvCWoMB2BNmEGUW5GH3/OAbWcwkXTU4h4zoaLktjM1lpGVPRtkFO9eKzBeoObY X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.149.145 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: devicetree-discuss@lists.ozlabs.org, linux-omap@vger.kernel.org, Benoit Cousson , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Create the sections describing the McBSP ports to be able to use them via DT. Signed-off-by: Peter Ujfalusi --- arch/arm/boot/dts/omap4.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 47 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 04cbbcb..258435f 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -295,5 +295,52 @@ interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; + + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@48096000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x48096000 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = <0 16 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; }; };