From patchwork Fri Aug 31 12:21:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 1393111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 14A213FDF5 for ; Fri, 31 Aug 2012 12:26:19 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T7QFs-0004h6-V0; Fri, 31 Aug 2012 12:23:21 +0000 Received: from eu1sys200aog115.obsmtp.com ([207.126.144.139]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1T7QEt-0004Jd-Ig for linux-arm-kernel@lists.infradead.org; Fri, 31 Aug 2012 12:22:21 +0000 Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUECscsaywMOJzfMZv1pr8OvDVAIIUm5A@postini.com; Fri, 31 Aug 2012 12:22:19 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 2A5B549; Fri, 31 Aug 2012 12:21:41 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id B96EC49; Fri, 31 Aug 2012 08:31:58 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 19EB924C2E5; Fri, 31 Aug 2012 14:22:02 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Fri, 31 Aug 2012 14:22:08 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette , Samuel Ortiz , Subject: [PATCH 4/4] clk: ux500: Define smp_twd clock for u8500 Date: Fri, 31 Aug 2012 14:21:31 +0200 Message-ID: <1346415691-13371-5-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com> References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.139 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Philippe Begnic , Linus Walleij , Lee Jones , Ulf Hansson , Srinidhi Kasagar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Ulf Hansson The smp_twd clock is based upon a prcmu_rate clock type for the PRCMU_ARMSS clock. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/u8500_clk.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 5c1fca1..ca4a25e 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -205,12 +205,16 @@ void u8500_clk_init(void) clk_register_clkdev(clk, "dsilp2", "dsilink.2"); clk_register_clkdev(clk, "dsilp2", "mcde"); + clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS, + CLK_IS_ROOT|CLK_GET_RATE_NOCACHE| + CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, NULL, "smp_twd"); + /* * FIXME: Add special handled PRCMU clocks here: - * 1. smp_twd, use PRCMU_ARMSS. - * 2. clk_arm, use PRCMU_ARMCLK. - * 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. - * 4. ab9540_clkout1yuv, see clkout0yuv + * 1. clk_arm, use PRCMU_ARMCLK. + * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. + * 3. ab9540_clkout1yuv, see clkout0yuv */ /* PRCC P-clocks */