From patchwork Sat Sep 1 03:55:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1394811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id E02DA40B02 for ; Sat, 1 Sep 2012 04:00:27 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T7epD-0007xb-1n; Sat, 01 Sep 2012 03:56:47 +0000 Received: from mail.df.lth.se ([194.47.250.12]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T7eow-0007vv-Jw for linux-arm-kernel@lists.infradead.org; Sat, 01 Sep 2012 03:56:33 +0000 Received: from mer.df.lth.se (mer.df.lth.se [194.47.250.37]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.df.lth.se (Postfix) with ESMTPS id 99D4A65D78; Sat, 1 Sep 2012 05:56:28 +0200 (CEST) Received: from mer.df.lth.se (triad@localhost.localdomain [127.0.0.1]) by mer.df.lth.se (8.14.3/8.14.3/Debian-9.4) with ESMTP id q813uS43024045; Sat, 1 Sep 2012 05:56:28 +0200 Received: (from triad@localhost) by mer.df.lth.se (8.14.3/8.14.3/Submit) id q813uSJI024044; Sat, 1 Sep 2012 05:56:28 +0200 From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org Subject: [PATCH 3/6 v2] ARM: plat-versatile: add DT support to FPGA IRQ controller Date: Sat, 1 Sep 2012 05:55:55 +0200 Message-Id: <1346471760-23993-3-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1346471760-23993-2-git-send-email-linus.walleij@linaro.org> References: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org> <1346471760-23993-2-git-send-email-linus.walleij@linaro.org> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.8 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [194.47.250.12 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Will Deacon , Linus Walleij , arm@kernel.org, Russell King , Pawel Moll X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This adds Device Tree probing support to the Versatile FPGA IRQ controller. Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Stop passing the Linux IRQ number in the DT node, bad idea. Register descriptors dynamically, and use whatever IRQ number base we get. Assume we will switch everything using this over to DT and live with it. --- .../devicetree/bindings/arm/versatile-fpga-irq.txt | 31 ++++++++++++++ arch/arm/plat-versatile/fpga-irq.c | 47 ++++++++++++++++++++++ arch/arm/plat-versatile/include/plat/fpga-irq.h | 2 + 3 files changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt new file mode 100644 index 0000000..9989eda --- /dev/null +++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt @@ -0,0 +1,31 @@ +* ARM Versatile FPGA interrupt controller + +One or more FPGA IRQ controllers can be synthesized in an ARM reference board +such as the Integrator or Versatile family. The output of these different +controllers are OR:ed together and fed to the CPU tile's IRQ input. Each +instance can handle up to 32 interrupts. + +Required properties: +- compatible: "arm,versatile-fpga-irq" +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: The number of cells to define the interrupts. Must be 1 + as the FPGA IRQ controller has no configuration options for interrupt + sources. The cell is a u32 and defines the interrupt number. +- reg: The register bank for the FPGA interrupt controller. +- clear-mask: a u32 number representing the mask written to clear all IRQs + on the controller at boot for example. +- valid-mask: a u32 number representing a bit mask determining which of + the interrupts are valid. Unconnected/unused lines are set to 0, and + the system till not make it possible for devices to request these + interrupts. + +Example: + +pic: pic@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x003fffff>; +}; diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index 6e70d03..1ca595c 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include #include @@ -14,6 +16,13 @@ #define IRQ_RAW_STATUS 0x04 #define IRQ_ENABLE_SET 0x08 #define IRQ_ENABLE_CLEAR 0x0c +#define INT_SOFT_SET 0x10 +#define INT_SOFT_CLEAR 0x14 +#define FIQ_STATUS 0x20 +#define FIQ_RAW_STATUS 0x24 +#define FIQ_ENABLE 0x28 +#define FIQ_ENABLE_SET 0x28 +#define FIQ_ENABLE_CLEAR 0x2C /** * struct fpga_irq_data - irq data container for the FPGA IRQ controller @@ -156,3 +165,41 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, fpga_irq_id++; } + +#ifdef CONFIG_OF +int __init fpga_irq_of_init(struct device_node *node, + struct device_node *parent) +{ + void __iomem *base; + u32 irq_start; + u32 clear_mask; + u32 valid_mask; + + if (WARN_ON(!node)) + return -ENODEV; + + base = of_iomap(node, 0); + WARN(!base, "unable to map fpga irq registers\n"); + + if (of_property_read_u32(node, "clear-mask", &clear_mask)) + clear_mask = 0; + + if (of_property_read_u32(node, "valid-mask", &valid_mask)) + valid_mask = 0; + + irq_start = irq_alloc_descs(-1, 0, fls(valid_mask), numa_node_id()); + if (WARN_ON(irq_start < 0)) + goto out_unmap; + + writel(clear_mask, base + IRQ_ENABLE_CLEAR); + writel(clear_mask, base + FIQ_ENABLE_CLEAR); + + fpga_irq_init(base, node->name, irq_start, -1, valid_mask, node); + + return 0; + +out_unmap: + iounmap(base); + return -EIO; +} +#endif diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h index 91bcfb6..1fac965 100644 --- a/arch/arm/plat-versatile/include/plat/fpga-irq.h +++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h @@ -7,5 +7,7 @@ struct pt_regs; void fpga_handle_irq(struct pt_regs *regs); void fpga_irq_init(void __iomem *, const char *, int, int, u32, struct device_node *node); +int fpga_irq_of_init(struct device_node *node, + struct device_node *parent); #endif