From patchwork Wed Sep 5 11:58:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 1409111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 4B3F840220 for ; Wed, 5 Sep 2012 12:04:43 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T9EHR-00053o-5A; Wed, 05 Sep 2012 12:00:26 +0000 Received: from na3sys009aog127.obsmtp.com ([74.125.149.107]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1T9EGC-0004ON-5e for linux-arm-kernel@lists.infradead.org; Wed, 05 Sep 2012 11:59:09 +0000 Received: from mail-gg0-f177.google.com ([209.85.161.177]) (using TLSv1) by na3sys009aob127.postini.com ([74.125.148.12]) with SMTP ID DSNKUEc+iagtdErFcwVp9GoZztltJqhxCPt3@postini.com; Wed, 05 Sep 2012 04:59:08 PDT Received: by ggnm2 with SMTP id m2so53267ggn.36 for ; Wed, 05 Sep 2012 04:59:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=J8BNPIUqZuytsA1U81MQtOPnrwvwHnfxs1vhyVhqNzE=; b=fOg9Zob1K4i7Mcqb92/HWHDEgvxd8kzpdw8K8Jc+b8kC8/QdtSpekTFgPdt9sJpkZj C+DTcBD85x6PPXVwi3AAclJhDlJxANcmUOmSL2B3DJx7K3RuQNYEwomPZOq3yfAMspyQ 8PmcGOH0VeiJwYCi1L4oUYytlpX5G3zB4t5lS34skcn5hVOF3DSEYcYdSu0zO3czx/TN 8ZNvQUOy5uOgdlRRc0e1RjY2zQZhFHtdOwBkBmC7Nh0rBxnHITbneM8oEXWJddpZYNzs jIqQN4kUYae6DuXo6Dd/PVUytOJsGoqEqIThFjS1jEICmCOXAG0Rxjtr1qgzQr/4G85s 2K2w== Received: by 10.236.186.73 with SMTP id v49mr22301403yhm.48.1346846345188; Wed, 05 Sep 2012 04:59:05 -0700 (PDT) Received: from barack.emea.dhcp.ti.com (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id h8sm1450364ank.9.2012.09.05.04.59.03 (version=SSLv3 cipher=OTHER); Wed, 05 Sep 2012 04:59:04 -0700 (PDT) From: Peter Ujfalusi To: Tony Lindgren , Benoit Cousson Subject: [PATCH v3 7/8] ARM/dts: omap5: Add McPDM and DMIC section to the dtsi file Date: Wed, 5 Sep 2012 14:58:55 +0300 Message-Id: <1346846336-27321-8-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1346846336-27321-1-git-send-email-peter.ujfalusi@ti.com> References: <1346846336-27321-1-git-send-email-peter.ujfalusi@ti.com> X-Gm-Message-State: ALoCoQn9CTEw3W74ZxPF3zsdzvQMSoSgt/rOTc5ue60Ej33opOaQbnaWHCr8AmA4nenRvd5/3tjQ X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.149.107 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: devicetree-discuss@lists.ozlabs.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org To be able to load the McPDM and DMIC driver when booted with device tree. Signed-off-by: Peter Ujfalusi --- arch/arm/boot/dts/omap5.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index aa97e93..9ac75b3 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -252,6 +252,26 @@ ti,hwmods = "kbd"; }; + mcpdm: mcpdm@40132000 { + compatible = "ti,omap4-mcpdm"; + reg = <0x40132000 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 112 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "mcpdm"; + }; + + dmic: dmic@4012e000 { + compatible = "ti,omap4-dmic"; + reg = <0x4012e000 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 114 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "dmic"; + }; + mcbsp1: mcbsp@40122000 { compatible = "ti,omap4-mcbsp"; reg = <0x40122000 0xff>, /* MPU private access */