From patchwork Wed Sep 5 19:28:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 1410451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 6F97A3FC71 for ; Wed, 5 Sep 2012 19:32:22 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T9LHi-0003b4-9A; Wed, 05 Sep 2012 19:29:10 +0000 Received: from wolverine01.qualcomm.com ([199.106.114.254]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T9LHc-0003aS-Pp for linux-arm-kernel@lists.infradead.org; Wed, 05 Sep 2012 19:29:06 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6826"; a="233224500" Received: from pdmz-ns-snip_115.254.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.115.254]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 05 Sep 2012 12:29:02 -0700 Received: from sboyd-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 0DFAC10004D5; Wed, 5 Sep 2012 12:29:02 -0700 (PDT) From: Stephen Boyd To: David Brown , Bryan Huntsman , Daniel Walker Subject: [PATCH 1/9] ARM: msm: Don't touch GIC registers outside of GIC code Date: Wed, 5 Sep 2012 12:28:51 -0700 Message-Id: <1346873339-10927-2-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.7.12.176.g3fc0e4c In-Reply-To: <1346873339-10927-1-git-send-email-sboyd@codeaurora.org> References: <1346873339-10927-1-git-send-email-sboyd@codeaurora.org> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.254 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The MSM code has some antiquated register writes to set up the PPIs to be edge triggered. Now that we have the percpu irq interface we don't need this code so let's remove it and update the percpu irq user (msm_timer) to set the irq type. Signed-off-by: Stephen Boyd --- arch/arm/mach-msm/board-msm8960.c | 13 ------------- arch/arm/mach-msm/board-msm8x60.c | 3 --- arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-msm/timer.c | 4 ++-- 4 files changed, 2 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 65f4a1d..bdafe79 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -55,24 +55,11 @@ static void __init msm8960_map_io(void) static void __init msm8960_init_irq(void) { - unsigned int i; gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE); - /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ - writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - if (machine_is_msm8960_rumi3()) writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); - - /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet - * as they are configured as level, which does not play nice with - * handle_percpu_irq. - */ - for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { - if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - irq_set_handler(i, handle_percpu_irq); - } } static struct platform_device *sim_devices[] __initdata = { diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index ad87207..64ae269 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -67,9 +67,6 @@ static void __init msm8x60_init_irq(void) of_irq_init(msm_dt_gic_match); #endif - /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ - writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - /* RUMI does not adhere to GIC spec by enabling STIs by default. * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. */ diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index e012dc8..2d791e6 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -22,17 +22,12 @@ #include #include -#include - #include "scm-boot.h" #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 #define SCSS_CPU1CORE_RESET 0xD80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 -/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ -#define GIC_PPI_EDGE_MASK 0xFFFFD7FF - extern void msm_secondary_startup(void); /* * control for which core is the next to come out of the secondary @@ -50,9 +45,6 @@ static inline int get_core_count(void) void __cpuinit platform_secondary_init(unsigned int cpu) { - /* Configure edge-triggered PPIs */ - writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 81280825..36bbc60 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) *__this_cpu_ptr(msm_evt.percpu_evt) = evt; clockevents_register_device(evt); - enable_percpu_irq(evt->irq, 0); + enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); return 0; } @@ -219,7 +219,7 @@ static void __init msm_timer_init(void) res = request_percpu_irq(ce->irq, msm_timer_interrupt, ce->name, msm_evt.percpu_evt); if (!res) { - enable_percpu_irq(ce->irq, 0); + enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_LOCAL_TIMERS local_timer_register(&msm_local_timer_ops); #endif