From patchwork Thu Sep 6 14:55:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 1417041 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 8AAA0DFFCF for ; Thu, 6 Sep 2012 16:36:32 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T9ehi-0002cR-Ds; Thu, 06 Sep 2012 16:13:18 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T9dVR-0001Wl-3h for linux-arm-kernel@lists.infradead.org; Thu, 06 Sep 2012 14:56:36 +0000 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 06 Sep 2012 07:57:52 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Thu, 06 Sep 2012 07:55:51 -0700 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Thu, 06 Sep 2012 07:55:51 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.264.0; Thu, 6 Sep 2012 07:56:21 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 06 Sep 2012 07:57:02 -0700 Received: from tbergstrom-lnx.Nvidia.com (dhcp-10-21-25-181.nvidia.com [10.21.25.181]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q86Etpl9001602; Thu, 6 Sep 2012 07:56:19 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver Subject: [PATCH 2/2] ARM: tegra: fix debugfs entry for Tegra30 Date: Thu, 6 Sep 2012 17:55:29 +0300 Message-ID: <1346943329-4898-2-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1346943329-4898-1-git-send-email-pdeschrijver@nvidia.com> References: <1346943329-4898-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Russell King , Stephen Warren , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Colin Cross , Olof Johansson , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Tegra30 has more powerdomains than Tegra20. The debugfs code did not take this into account. Signed-off-by: Peter De Schrijver --- arch/arm/mach-tegra/powergate.c | 40 ++++++++++++++++++++++++++++++++++---- 1 files changed, 35 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 27aee4a..de0662d 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -199,7 +199,9 @@ int __init tegra_powergate_init(void) #ifdef CONFIG_DEBUG_FS -static const char * const powergate_name[] = { +static const char * const *powergate_name; + +static const char * const powergate_name_t20[] = { [TEGRA_POWERGATE_CPU] = "cpu", [TEGRA_POWERGATE_3D] = "3d", [TEGRA_POWERGATE_VENC] = "venc", @@ -209,6 +211,23 @@ static const char * const powergate_name[] = { [TEGRA_POWERGATE_MPE] = "mpe", }; +static const char * const powergate_name_t30[] = { + [TEGRA_POWERGATE_CPU] = "cpu0", + [TEGRA_POWERGATE_3D] = "3d0", + [TEGRA_POWERGATE_VENC] = "venc", + [TEGRA_POWERGATE_VDEC] = "vdec", + [TEGRA_POWERGATE_PCIE] = "pcie", + [TEGRA_POWERGATE_L2] = "l2", + [TEGRA_POWERGATE_MPE] = "mpe", + [TEGRA_POWERGATE_HEG] = "heg", + [TEGRA_POWERGATE_SATA] = "sata", + [TEGRA_POWERGATE_CPU1] = "cpu1", + [TEGRA_POWERGATE_CPU2] = "cpu2", + [TEGRA_POWERGATE_CPU3] = "cpu3", + [TEGRA_POWERGATE_CELP] = "celp", + [TEGRA_POWERGATE_3D1] = "3d1", +}; + static int powergate_show(struct seq_file *s, void *data) { int i; @@ -238,10 +257,21 @@ int __init tegra_powergate_debugfs_init(void) { struct dentry *d; - d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, - &powergate_fops); - if (!d) - return -ENOMEM; + switch (tegra_chip_id) { + case TEGRA20: + powergate_name = powergate_name_t20; + break; + case TEGRA30: + powergate_name = powergate_name_t30; + break; + } + + if (powergate_name) { + d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, + &powergate_fops); + if (!d) + return -ENOMEM; + } return 0; }