| Message ID | 1347008955-21310-1-git-send-email-kishon@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Kishon, Benoît, On Fri, 7 Sep 2012, Kishon Vijay Abraham I wrote: > Made *ocp2scp_usb_phy_phy_48m* as the main_clk for ocp2scp. Since this > ocp2scp module does not have any fck but does have a single opt_clock, > it is added as the main_clk for ocp2scp. Also removed phy_48m as the > optional clock since it is now made as the main clock. By this the > driver need not enable/disable phy_48m clk separately and > runtime_get/runtime_put will take care of that. Looking at this patch, it doesn't seem to make sense from a hardware point of view. If you look at the OMAP4430 TRM Rev. AE, Table 23-1166 "Clocks and Resets", the 48MHz clock input is listed as an "Optional functional clock". The main functional clock is listed as "INIT_960M_FCLK", which according to the same TRM, Section 3.6.3.9.1 "Overview", is an alias for the clock we call "dpll_usb_clkdcoldo_ck". So if any clock should be the main functional clock in the hwmod data, shouldn't it be dpll_usb_clkdcoldo_ck? The goal with the hwmod data is/was to have it match the hardware. ... More to the point, I guess I don't see what the problem is with adding a few lines to the ocp2scp driver to control the "phy_48m" optional clock via the clock framework. Is there some reason why you couldn't prepare & enable it after the pm_runtime_get_*(), and disable and unprepare it before the pm_runtime_put_*() ? - Paul
Hi, On Wed, Sep 12, 2012 at 3:58 AM, Paul Walmsley <paul@pwsan.com> wrote: > Hi Kishon, Benoît, > > On Fri, 7 Sep 2012, Kishon Vijay Abraham I wrote: > >> Made *ocp2scp_usb_phy_phy_48m* as the main_clk for ocp2scp. Since this >> ocp2scp module does not have any fck but does have a single opt_clock, >> it is added as the main_clk for ocp2scp. Also removed phy_48m as the >> optional clock since it is now made as the main clock. By this the >> driver need not enable/disable phy_48m clk separately and >> runtime_get/runtime_put will take care of that. > > Looking at this patch, it doesn't seem to make sense from a hardware point > of view. If you look at the OMAP4430 TRM Rev. AE, Table 23-1166 "Clocks > and Resets", the 48MHz clock input is listed as an "Optional functional > clock". The main functional clock is listed as "INIT_960M_FCLK", which > according to the same TRM, Section 3.6.3.9.1 "Overview", is an alias for > the clock we call "dpll_usb_clkdcoldo_ck". > > So if any clock should be the main functional clock in the hwmod data, > shouldn't it be dpll_usb_clkdcoldo_ck? The goal with the hwmod data > is/was to have it match the hardware. > > ... > > More to the point, I guess I don't see what the problem is with > adding a few lines to the ocp2scp driver to control the "phy_48m" optional It should be added in omap-usb2 driver rather. > clock via the clock framework. Is there some reason why you > couldn't prepare & enable it after the pm_runtime_get_*(), > and disable and unprepare it before the pm_runtime_put_*() ? We have omap-usb2 driver that is used for both omap4 and omap5. But this 48m clock is used only in omap4. And we dint have any *main_clk* in the ocp2scp_usb_phy_hwmod. So in order avoid some checks in the omap-usb2 driver, we added 48m clk as the main clock of ocp2scp_usb_phy_hwmod. Thanks Kishon
Hi Paul, On 09/12/2012 12:28 AM, Paul Walmsley wrote: > Hi Kishon, Benoît, > > On Fri, 7 Sep 2012, Kishon Vijay Abraham I wrote: > >> Made *ocp2scp_usb_phy_phy_48m* as the main_clk for ocp2scp. Since this >> ocp2scp module does not have any fck but does have a single opt_clock, >> it is added as the main_clk for ocp2scp. Also removed phy_48m as the >> optional clock since it is now made as the main clock. By this the >> driver need not enable/disable phy_48m clk separately and >> runtime_get/runtime_put will take care of that. > > Looking at this patch, it doesn't seem to make sense from a hardware point > of view. If you look at the OMAP4430 TRM Rev. AE, Table 23-1166 "Clocks > and Resets", the 48MHz clock input is listed as an "Optional functional > clock". The main functional clock is listed as "INIT_960M_FCLK", which > according to the same TRM, Section 3.6.3.9.1 "Overview", is an alias for > the clock we call "dpll_usb_clkdcoldo_ck". > > So if any clock should be the main functional clock in the hwmod data, > shouldn't it be dpll_usb_clkdcoldo_ck? The goal with the hwmod data > is/was to have it match the hardware. In this case, the ocp2scp IP is just the *bus controller* to access the real USB_UTMI_PHY IP. The TRM diagram does not show that level of detail unfortunately. You can check the PRCM spec (Figure 78 : CD_L3_INIT_USB clock scheme) to see the two modules. So considering phy_48m as the main clock is still correct for the ocp2scp IP. The INIT_960M_FCLK will be a fck associated with the child of the ocp2scp nodes which is the usb_phy. Upgrading the opt_clk to fck does make sense as soon as we don't have any other functional clock and as soon as this clock is *mandatory*. The optional aspect in that case is just a wrong PRCM naming for a clock that is mandatory. It is similar to the DSS case that does have only optional clocks that are mandatory. I do agree that we must stick to the HW definition as far as we can. But the optional attribute is something that is wrong/inaccurate for a couple of IPs. HW folks agreed on that point and will fix that in the future. Regards, Benoit
On Thu, 13 Sep 2012, Benoit Cousson wrote: > In this case, the ocp2scp IP is just the *bus controller* to access the > real USB_UTMI_PHY IP. > > The TRM diagram does not show that level of detail unfortunately. You > can check the PRCM spec (Figure 78 : CD_L3_INIT_USB clock scheme) to see > the two modules. > > So considering phy_48m as the main clock is still correct for the > ocp2scp IP. > > The INIT_960M_FCLK will be a fck associated with the child of the > ocp2scp nodes which is the usb_phy. > > Upgrading the opt_clk to fck does make sense as soon as we don't have > any other functional clock and as soon as this clock is *mandatory*. The > optional aspect in that case is just a wrong PRCM naming for a clock > that is mandatory. It is similar to the DSS case that does have only > optional clocks that are mandatory. > > I do agree that we must stick to the HW definition as far as we can. But > the optional attribute is something that is wrong/inaccurate for a > couple of IPs. HW folks agreed on that point and will fix that in the > future. Okay so is this an Acked-by for this patch? :-) If so I'll take it. - Paul
On Thu, 13 Sep 2012, Paul Walmsley wrote: > Okay so is this an Acked-by for this patch? :-) > > If so I'll take it. Just realized that's what your reply was, so have queued the patch for 3.7. - Paul
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 242aee4..e8e5405 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2503,14 +2503,11 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { }; /* ocp2scp_usb_phy */ -static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { - { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, -}; - static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", .class = &omap44xx_ocp2scp_hwmod_class, .clkdm_name = "l3_init_clkdm", + .main_clk = "ocp2scp_usb_phy_phy_48m", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, @@ -2518,8 +2515,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .opt_clks = ocp2scp_usb_phy_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), }; /*