From patchwork Wed Sep 12 23:01:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Brown X-Patchwork-Id: 1447111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (unknown [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id C8EAEDF238 for ; Wed, 12 Sep 2012 23:15:56 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TBvwX-0000ab-1j; Wed, 12 Sep 2012 23:02:01 +0000 Received: from wolverine02.qualcomm.com ([199.106.114.251]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TBvwS-0000Zo-Sa for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2012 23:01:57 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6833"; a="233698645" Received: from pdmz-ns-snip_115_219.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.115.219]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 12 Sep 2012 16:01:54 -0700 Received: from codeaurora.org (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 914F410004AA; Wed, 12 Sep 2012 16:01:54 -0700 (PDT) From: David Brown To: Marc Zyngier Subject: [PATCH 1/2] ARM: SoC: convert MSM SMP to SoC descriptor Date: Wed, 12 Sep 2012 16:01:39 -0700 Message-Id: <1347490900-8409-1-git-send-email-davidb@codeaurora.org> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347461906-13527-7-git-send-email-arnd@arndb.de> References: <1347461906-13527-7-git-send-email-arnd@arndb.de> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.251 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, David Brown , Arnd Bergmann , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Marc Zyngier Convert MSM SMP platforms to use the SoC descriptor to provide their SMP and CPU hotplug operations. Cc: David Brown Signed-off-by: Marc Zyngier Signed-off-by: Arnd Bergmann --- This is an adaptation of this change on top of the msm-for-3.7 tree I recently sent out a pull request for. The only real change is to resolve the conflicts with the simplified board files. arch/arm/mach-msm/board-dt-8660.c | 2 ++ arch/arm/mach-msm/board-dt-8960.c | 2 ++ arch/arm/mach-msm/core.h | 2 ++ arch/arm/mach-msm/hotplug.c | 18 +++--------------- arch/arm/mach-msm/platsmp.c | 19 +++++++++++++++---- 5 files changed, 24 insertions(+), 19 deletions(-) create mode 100644 arch/arm/mach-msm/core.h diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c index f77f57f..e5643f6 100644 --- a/arch/arm/mach-msm/board-dt-8660.c +++ b/arch/arm/mach-msm/board-dt-8660.c @@ -20,6 +20,7 @@ #include #include "common.h" +#include "core.h" static const struct of_device_id msm_dt_gic_match[] __initconst = { { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, @@ -53,6 +54,7 @@ static const char *msm8x60_fluid_match[] __initdata = { }; DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") + .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8x60_io, .init_irq = msm8x60_init_irq, .handle_irq = gic_handle_irq, diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c index 8df99b8..139d61b 100644 --- a/arch/arm/mach-msm/board-dt-8960.c +++ b/arch/arm/mach-msm/board-dt-8960.c @@ -18,6 +18,7 @@ #include #include "common.h" +#include "core.h" static const struct of_device_id msm_dt_gic_match[] __initconst = { { .compatible = "qcom,msm-qgic2", .data = gic_of_init }, @@ -40,6 +41,7 @@ static const char * const msm8960_dt_match[] __initconst = { }; DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") + .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8960_io, .init_irq = msm_dt_init_irq, .timer = &msm_dt_timer, diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h new file mode 100644 index 0000000..a9bab53 --- /dev/null +++ b/arch/arm/mach-msm/core.h @@ -0,0 +1,2 @@ +extern struct smp_operations msm_smp_ops; +extern void msm_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c index a446fc1..d0f79e8 100644 --- a/arch/arm/mach-msm/hotplug.c +++ b/arch/arm/mach-msm/hotplug.c @@ -13,6 +13,8 @@ #include #include +#include "core.h" + extern volatile int pen_release; static inline void cpu_enter_lowpower(void) @@ -57,17 +59,12 @@ static inline void platform_do_lowpower(unsigned int cpu) } } -int platform_cpu_kill(unsigned int cpu) -{ - return 1; -} - /* * platform-specific code to shutdown a CPU * * Called with IRQs disabled */ -void platform_cpu_die(unsigned int cpu) +void msm_cpu_die(unsigned int cpu) { /* * we're ready for shutdown now, so do it @@ -81,12 +78,3 @@ void platform_cpu_die(unsigned int cpu) */ cpu_leave_lowpower(); } - -int platform_cpu_disable(unsigned int cpu) -{ - /* - * we don't allow CPU 0 to be shutdown (it is still too special - * e.g. clock tick interrupts) - */ - return cpu == 0 ? -EPERM : 0; -} diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index b119f99..313bd7d 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -23,6 +23,7 @@ #include #include "scm-boot.h" +#include "core.h" #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 #define SCSS_CPU1CORE_RESET 0xD80 @@ -43,7 +44,7 @@ static inline int get_core_count(void) return ((read_cpuid_id() >> 4) & 3) + 1; } -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit msm_secondary_init(unsigned int cpu) { /* * if any interrupts are already enabled for the primary @@ -85,7 +86,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu) "address\n"); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; static int cold_boot_done; @@ -145,7 +146,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * does not support the ARM SCU, so just set the possible cpu mask to * NR_CPUS. */ -void __init smp_init_cpus(void) +static void __init msm_smp_init_cpus(void) { unsigned int i, ncores = get_core_count(); @@ -161,6 +162,16 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init msm_smp_prepare_cpus(unsigned int max_cpus) { } + +struct smp_operations msm_smp_ops __initdata = { + .smp_init_cpus = msm_smp_init_cpus, + .smp_prepare_cpus = msm_smp_prepare_cpus, + .smp_secondary_init = msm_secondary_init, + .smp_boot_secondary = msm_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = msm_cpu_die, +#endif +};