From patchwork Fri Sep 14 16:11:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 1459441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 9C766DF280 for ; Fri, 14 Sep 2012 16:15:11 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TCYUm-0002V1-IK; Fri, 14 Sep 2012 16:11:56 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TCYUX-0002SS-9v for linux-arm-kernel@lists.infradead.org; Fri, 14 Sep 2012 16:11:43 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 0807F644C; Fri, 14 Sep 2012 10:11:57 -0600 (MDT) Received: from localhost.localdomain (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id A04F7E460E; Fri, 14 Sep 2012 10:11:38 -0600 (MDT) From: Stephen Warren To: Stephen Warren , Mark Brown , Liam Girdwood , Grant Likely Subject: [PATCH RESEND 3/5] ARM: tegra: apbio: remove support of legacy DMA driver based access Date: Fri, 14 Sep 2012 10:11:27 -0600 Message-Id: <1347639089-2520-3-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1347639089-2520-1-git-send-email-swarren@wwwdotorg.org> References: <1347639089-2520-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.4 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: alsa-devel@alsa-project.org, Stephen Warren , Laxman Dewangan , linux-tegra@vger.kernel.org, spi-devel-general@lists.sourceforge.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Laxman Dewangan Remove the support code which uses the legacy APB DMA driver for accessing the apbio register. The driver will use the dmaengine based APB DMA driver for accessing apbio register. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/apbio.c | 118 +------------------------------------------ 1 files changed, 1 insertions(+), 117 deletions(-) diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index 643a378..b5015d0 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c @@ -28,7 +28,7 @@ #include "apbio.h" -#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA) +#if defined(CONFIG_TEGRA20_APB_DMA) static DEFINE_MUTEX(tegra_apb_dma_lock); static u32 *tegra_apb_bb; static dma_addr_t tegra_apb_bb_phys; @@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait); static u32 tegra_apb_readl_direct(unsigned long offset); static void tegra_apb_writel_direct(u32 value, unsigned long offset); -#if defined(CONFIG_TEGRA_SYSTEM_DMA) -static struct tegra_dma_channel *tegra_apb_dma; - -bool tegra_apb_init(void) -{ - struct tegra_dma_channel *ch; - - mutex_lock(&tegra_apb_dma_lock); - - /* Check to see if we raced to setup */ - if (tegra_apb_dma) - goto out; - - ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT | - TEGRA_DMA_SHARED); - - if (!ch) - goto out_fail; - - tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), - &tegra_apb_bb_phys, GFP_KERNEL); - if (!tegra_apb_bb) { - pr_err("%s: can not allocate bounce buffer\n", __func__); - tegra_dma_free_channel(ch); - goto out_fail; - } - - tegra_apb_dma = ch; -out: - mutex_unlock(&tegra_apb_dma_lock); - return true; - -out_fail: - mutex_unlock(&tegra_apb_dma_lock); - return false; -} - -static void apb_dma_complete(struct tegra_dma_req *req) -{ - complete(&tegra_apb_wait); -} - -static u32 tegra_apb_readl_using_dma(unsigned long offset) -{ - struct tegra_dma_req req; - int ret; - - if (!tegra_apb_dma && !tegra_apb_init()) - return tegra_apb_readl_direct(offset); - - mutex_lock(&tegra_apb_dma_lock); - req.complete = apb_dma_complete; - req.to_memory = 1; - req.dest_addr = tegra_apb_bb_phys; - req.dest_bus_width = 32; - req.dest_wrap = 1; - req.source_addr = offset; - req.source_bus_width = 32; - req.source_wrap = 4; - req.req_sel = TEGRA_DMA_REQ_SEL_CNTR; - req.size = 4; - - INIT_COMPLETION(tegra_apb_wait); - - tegra_dma_enqueue_req(tegra_apb_dma, &req); - - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb read dma timed out")) { - tegra_dma_dequeue_req(tegra_apb_dma, &req); - *(u32 *)tegra_apb_bb = 0; - } - - mutex_unlock(&tegra_apb_dma_lock); - return *((u32 *)tegra_apb_bb); -} - -static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) -{ - struct tegra_dma_req req; - int ret; - - if (!tegra_apb_dma && !tegra_apb_init()) { - tegra_apb_writel_direct(value, offset); - return; - } - - mutex_lock(&tegra_apb_dma_lock); - *((u32 *)tegra_apb_bb) = value; - req.complete = apb_dma_complete; - req.to_memory = 0; - req.dest_addr = offset; - req.dest_wrap = 4; - req.dest_bus_width = 32; - req.source_addr = tegra_apb_bb_phys; - req.source_bus_width = 32; - req.source_wrap = 1; - req.req_sel = TEGRA_DMA_REQ_SEL_CNTR; - req.size = 4; - - INIT_COMPLETION(tegra_apb_wait); - - tegra_dma_enqueue_req(tegra_apb_dma, &req); - - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb write dma timed out")) - tegra_dma_dequeue_req(tegra_apb_dma, &req); - - mutex_unlock(&tegra_apb_dma_lock); -} - -#else static struct dma_chan *tegra_apb_dma_chan; static struct dma_slave_config dma_sconfig; @@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) pr_err("error in writing offset 0x%08lx using dma\n", offset); mutex_unlock(&tegra_apb_dma_lock); } -#endif #else #define tegra_apb_readl_using_dma tegra_apb_readl_direct #define tegra_apb_writel_using_dma tegra_apb_writel_direct