| Message ID | 1347694914-1457-1-git-send-email-rvaswani@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Sep 15, 2012 at 12:41:53AM -0700, Rohit Vaswani wrote: > On some hardware, the timer deasserts the interrupt when a > new TVAL is written only when the enable bit is cleared. > Hence explicitly disable the timer and then program the > TVAL followed by enabling the timer. > If this order is not followed, there are chances that > you would not receive any timer interrupts. It's a little unclear to me who you intend to take this patch. In the To field, you've listed Marc, the MSM maintainers, as well as Russell. The MSM tree doesn't really make sense, since this is general ARM code. Marc would make sense if you depend on an active patch series he is working on, so he could include it. I'm guessing you meant it for Russell, though, and the rest of us as CCs. Thanks, David
On 9/15/2012 10:00 AM, David Brown wrote: > On Sat, Sep 15, 2012 at 12:41:53AM -0700, Rohit Vaswani wrote: >> On some hardware, the timer deasserts the interrupt when a >> new TVAL is written only when the enable bit is cleared. >> Hence explicitly disable the timer and then program the >> TVAL followed by enabling the timer. >> If this order is not followed, there are chances that >> you would not receive any timer interrupts. > It's a little unclear to me who you intend to take this patch. In the > To field, you've listed Marc, the MSM maintainers, as well as Russell. > The MSM tree doesn't really make sense, since this is general ARM > code. Marc would make sense if you depend on an active patch series > he is working on, so he could include it. > > I'm guessing you meant it for Russell, though, and the rest of us as > CCs. Yes, thanks for pointing that out. Sorry if the headers were confusing, I will be more mindful of this next time. > > Thanks, > David > Thanks, Rohit Vaswani
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index c04c2a6..8672a75 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c @@ -206,9 +206,10 @@ static inline void set_next_event(const int access, unsigned long evt) { unsigned long ctrl; ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); - ctrl |= ARCH_TIMER_CTRL_ENABLE; - ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; + ctrl &= ~(ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK); + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt); + ctrl |= ARCH_TIMER_CTRL_ENABLE; arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); }
On some hardware, the timer deasserts the interrupt when a new TVAL is written only when the enable bit is cleared. Hence explicitly disable the timer and then program the TVAL followed by enabling the timer. If this order is not followed, there are chances that you would not receive any timer interrupts. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> --- arch/arm/kernel/arch_timer.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-)