From patchwork Tue Sep 25 19:19:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1506421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 5800340079 for ; Tue, 25 Sep 2012 19:22:25 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TGag8-0007CR-Sx; Tue, 25 Sep 2012 19:20:20 +0000 Received: from eu1sys200aog120.obsmtp.com ([207.126.144.149]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1TGag4-0007CD-Qj for linux-arm-kernel@lists.infradead.org; Tue, 25 Sep 2012 19:20:18 +0000 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob120.postini.com ([207.126.147.11]) with SMTP ID DSNKUGID5VhwxipkMFI/UJmYrriDwFq68gIA@postini.com; Tue, 25 Sep 2012 19:20:16 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9984E9D; Tue, 25 Sep 2012 19:11:44 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CF314B78; Tue, 25 Sep 2012 19:19:58 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 2641624C07C; Tue, 25 Sep 2012 21:19:48 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 25 Sep 2012 21:19:57 +0200 From: Linus Walleij To: Subject: [PATCH] ARM: GIC: dont warn on pre-allocated IRQ descs Date: Tue, 25 Sep 2012 21:19:54 +0200 Message-ID: <1348600794-2395-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.149 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Anmar Oueja , Grant Likely , Linus Walleij , Rob Herring , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Linus Walleij Currently, if you try to turn on CONFIG_SPARSE_IRQS for a platform using the GIC, you will get this in your face: ------------[ cut here ]------------ WARNING: at /home/elinwal/linux-stericsson/arch/arm/common/gic.c:713 gic_init_bases+0xe8/0x290() Cannot allocate irq_descs @ IRQ16, assuming pre-allocated Modules linked in: [] (unwind_backtrace+0x0/0xf8) from [] (warn_slowpath_common+0x4c/0x64) [] (warn_slowpath_common+0x4c/0x64) from [] (warn_slowpath_fmt+0x30/0x40) [] (warn_slowpath_fmt+0x30/0x40) from [] (gic_init_bases+0xe8/0x290) [] (gic_init_bases+0xe8/0x290) from [] (ux500_init_irq+0xb0/0xfc) [] (ux500_init_irq+0xb0/0xfc) from [] (init_IRQ+0x14/0x1c) [] (init_IRQ+0x14/0x1c) from [] (start_kernel+0x198/0x2ec) [] (start_kernel+0x198/0x2ec) from [<00008044>] (0x8044) ---[ end trace 1b75b31a2719ed1c ]--- This is because the GIC tries to allocate fresh IRQ descs for its IRQs, and that would work with non-sparse IRQs but fails with sparse IRQs because the .nr_irqs from the platform always get pre-allocated at boot time. The allocation will succeed if the platform define .nr_irqs to 0 as an ideal device tree platform would do, but I think it is a bit thick to require that every platform that wants to use sparse IRQs must first or simultaneously switch to device tree. So make this to a simple pr_debug(). Cc: Arnd Bergmann Cc: Rob Herring Cc: Grant Likely Signed-off-by: Linus Walleij --- arch/arm/common/gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index aa52699..fcda633 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -707,7 +707,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id()); if (IS_ERR_VALUE(irq_base)) { - WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", + pr_debug("Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", irq_start); irq_base = irq_start; }