From patchwork Wed Sep 26 16:02:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 1510091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id C6C2ADF238 for ; Wed, 26 Sep 2012 16:06:31 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TGu6H-0001F4-Vr; Wed, 26 Sep 2012 16:04:38 +0000 Received: from mail.free-electrons.com ([88.190.12.23]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TGu56-0000qi-4b for linux-arm-kernel@lists.infradead.org; Wed, 26 Sep 2012 16:03:26 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id DE523188; Wed, 26 Sep 2012 18:03:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 shortcircuit=no autolearn=ham version=3.3.1 Received: from localhost (tra42-5-83-152-246-54.fbx.proxad.net [83.152.246.54]) by mail.free-electrons.com (Postfix) with ESMTPSA id AD2381B6; Wed, 26 Sep 2012 18:02:53 +0200 (CEST) From: Gregory CLEMENT To: Jason Cooper , Andrew Lunn , Gregory Clement , Russell King Subject: [PATCH V5 6/6] arm: l2x0: add aurora related properties to OF binding Date: Wed, 26 Sep 2012 18:02:50 +0200 Message-Id: <1348675370-16359-7-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1348675370-16359-1-git-send-email-gregory.clement@free-electrons.com> References: <1348675370-16359-1-git-send-email-gregory.clement@free-electrons.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.8 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Lior Amsalem , Ike Pan , Will Deacon , Nadav Haklai , Ian Molton , David Marlin , Yehuda Yitschak , Jani Monoses , Tawfik Bayouk , Dan Frazier , Barry Song <21cnbao@gmail.com>, Eran Ben-Avi , Li Li , Russell King , Leif Lindholm , Sebastian Hesselbarth , Arnd Bergmann , Jon Masters , Rob Herring , Ben Dooks , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Chris Van Hoof , Nicolas Pitre , Grant Likely , Maen Suleiman , Shadi Ammouri , Olof Johansson X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Aurora is a L2 Cache Controller designed to be compatible with the L2x0 Cache Controller. L2X0 OF bindings are extended to support some specificity of Aurora (no cache id part number available through hardware, always write through mode, choice between outer cache and system cache). Signed-off-by: Gregory CLEMENT Signed-off-by: Yehuda Yitschak Tested-and-reviewed-by: Lior Amsalem Acked-by: Arnd Bergmann Cc: Grant Likely Cc: Rob Herring Cc: Russell King Cc: Barry Song <21cnbao@gmail.com> Cc: Will Deacon Cc: Arnd Bergmann Cc: Olof Johansson --- Documentation/devicetree/bindings/arm/l2cc.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 7ca5216..76b0ee6 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -10,6 +10,12 @@ Required properties: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" + "marvell,aurora-system-cache": Marvell Controller designed to be + compatible with the ARM one, with system cache mode (meaning + maintenance operations on L1 are broadcasted to the L2 and L2 + performs the same operation). + "marvell,"aurora-outer-cache: Marvell Controller designed to be + compatible with the ARM one with outer cache mode. - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped @@ -29,6 +35,9 @@ Optional properties: filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - interrupts : 1 combined interrupt. +- cache-id-part: cache id part number to be used if it is not present + on hardware +- wt-override: If present then L2 is forced to Write through mode Example: