From patchwork Wed Sep 26 21:40:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Baatz X-Patchwork-Id: 1511001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 04B84DF238 for ; Wed, 26 Sep 2012 21:43:39 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TGzMi-00037P-TI; Wed, 26 Sep 2012 21:41:56 +0000 Received: from mail-wg0-f49.google.com ([74.125.82.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TGzMR-00035o-Td for linux-arm-kernel@lists.infradead.org; Wed, 26 Sep 2012 21:41:41 +0000 Received: by wgbdt14 with SMTP id dt14so588265wgb.18 for ; Wed, 26 Sep 2012 14:41:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=yqAT5TIsyuPAG46R89f3aTRybko8tRqc7lwVhvwIcQ4=; b=BGlaPlxh6f27liDD/BOhaFmBUPeLyg4aSocvb32Z8fDH/C3Sq8lrYVm57I5nUIm+NR xmqWnN6WBa3Vkh7OkyxUsUkpnTzbqnhcJfE72RXQaKphSaD1OsZWVxDSvS31yF+8QOrN yw8iigokBpuE3441cEe9VaYHbtkH9XvEYBjfM0n4YzDrXLM/y59LJunM+HR5dBKCgFDc YrOK9+QTbeyWnpTC9jQ68AVkNVv7LOFhCgumVKmA+WZurddq6bDExS9rsL/s2GQDOKCF FKm38tznxiYNIH7QxOvGzx9sKilQTO8wgKrHz5x7EL6CQgDeiqzviAqEPktEIYDFnAQE 13mw== Received: by 10.180.105.6 with SMTP id gi6mr3958305wib.4.1348695697924; Wed, 26 Sep 2012 14:41:37 -0700 (PDT) Received: from gandalf.schnuecks.de (p5DE8D84E.dip.t-dialin.net. [93.232.216.78]) by mx.google.com with ESMTPS id ct3sm27807327wib.5.2012.09.26.14.41.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 26 Sep 2012 14:41:37 -0700 (PDT) Received: by gandalf.schnuecks.de (Postfix, from userid 500) id 7E22440120; Wed, 26 Sep 2012 23:41:36 +0200 (CEST) From: Simon Baatz To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] ARM: remove unnecessary flush of anon pages in flush(_kernel)_dcache_page() Date: Wed, 26 Sep 2012 23:40:59 +0200 Message-Id: <1348695659-27603-3-git-send-email-gmbnomis@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1348695659-27603-1-git-send-email-gmbnomis@gmail.com> References: <1348695659-27603-1-git-send-email-gmbnomis@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (gmbnomis[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: catalin.marinas@arm.com, linux@arm.linux.org.uk, jason@lakedaemon.net, andrew@lunn.ch X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On non-aliasing VIPT D-caches, there is no need to flush the kernel mapping of anon pages in flush_kernel_dcache_page() and flush_dcache_page() directly. If the page is mapped as executable later, the necessary D/I-cache flush will be done in __sync_icache_dcache(). Signed-off-by: Simon Baatz Cc: Catalin Marinas Cc: Russell King --- arch/arm/mm/flush.c | 60 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 982db2f..077c8fd 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -219,15 +219,18 @@ void __flush_kernel_dcache_page(struct page *page) mapping = page_mapping(page); - if (!cache_ops_need_broadcast() && - mapping && !mapping_mapped(mapping)) - clear_bit(PG_dcache_clean, &page->flags); - else { - __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); - if (mapping && !cache_is_vivt()) - __flush_icache_all(); - set_bit(PG_dcache_clean, &page->flags); + if (!cache_ops_need_broadcast()) { + if ((mapping && !mapping_mapped(mapping)) || + (!mapping && cache_is_vipt_nonaliasing())) { + clear_bit(PG_dcache_clean, &page->flags); + return; + } } + + __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); + if (mapping && !cache_is_vivt()) + __flush_icache_all(); + set_bit(PG_dcache_clean, &page->flags); } EXPORT_SYMBOL(__flush_kernel_dcache_page); @@ -296,16 +299,20 @@ void __sync_icache_dcache(pte_t pteval) * of this page. * * We have three cases to consider: - * - VIPT non-aliasing cache: fully coherent so nothing required. + * - VIPT non-aliasing cache: + * D-cache: fully coherent so nothing required. + * I-cache: Ensure I/D coherency in case of an already mapped page; + * __sync_icache_dcache() will handle the other cases. + * - VIPT aliasing: + * D-cache: need to handle one alias in our current VM view. + * I-cache: same as VIPT non-aliasing cache * - VIVT: fully aliasing, so we need to handle every alias in our * current VM view. - * - VIPT aliasing: need to handle one alias in our current VM view. * - * If we need to handle aliasing: - * If the page only exists in the page cache and there are no user - * space mappings, we can be lazy and remember that we may have dirty - * kernel cache lines for later. Otherwise, we assume we have - * aliasing mappings. + * If the page only exists in the page cache and there are no user + * space mappings, we can be lazy and remember that we may have dirty + * kernel cache lines for later. Otherwise, we assume we have + * aliasing mappings. * * Note that we disable the lazy flush for SMP configurations where * the cache maintenance operations are not automatically broadcasted. @@ -323,17 +330,20 @@ void flush_dcache_page(struct page *page) mapping = page_mapping(page); - if (!cache_ops_need_broadcast() && - mapping && !mapping_mapped(mapping)) - clear_bit(PG_dcache_clean, &page->flags); - else { - __flush_dcache_page(mapping, page); - if (mapping && cache_is_vivt()) - __flush_dcache_aliases(mapping, page); - else if (mapping) - __flush_icache_all(); - set_bit(PG_dcache_clean, &page->flags); + if (!cache_ops_need_broadcast()) { + if ((mapping && !mapping_mapped(mapping)) || + (!mapping && cache_is_vipt_nonaliasing())) { + clear_bit(PG_dcache_clean, &page->flags); + return; + } } + + __flush_dcache_page(mapping, page); + if (mapping && cache_is_vivt()) + __flush_dcache_aliases(mapping, page); + else if (mapping) + __flush_icache_all(); + set_bit(PG_dcache_clean, &page->flags); } EXPORT_SYMBOL(flush_dcache_page);