From patchwork Tue Oct 2 12:03:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 1536901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 59304DFFAD for ; Tue, 2 Oct 2012 12:13:36 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TJ1JY-00064u-Ar; Tue, 02 Oct 2012 12:11:04 +0000 Received: from mga11.intel.com ([192.55.52.93]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TJ1JU-00064g-B6 for linux-arm-kernel@lists.infradead.org; Tue, 02 Oct 2012 12:11:01 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 02 Oct 2012 05:10:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.80,523,1344236400"; d="scan'208";a="229498419" Received: from vkoul-udesk3.iind.intel.com (HELO [10.223.84.41]) ([10.223.84.41]) by fmsmga002.fm.intel.com with ESMTP; 02 Oct 2012 05:10:53 -0700 Subject: Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC From: Vinod Koul To: Matt Porter In-Reply-To: <20121001163955.GO5641@beef> References: <1348152226-13588-1-git-send-email-mporter@ti.com> <1348152226-13588-9-git-send-email-mporter@ti.com> <20120921184721.GD31374@n2100.arm.linux.org.uk> <1348738868.1648.13.camel@vkoul-udesk3> <20121001163955.GO5641@beef> Date: Tue, 02 Oct 2012 17:33:43 +0530 Message-ID: <1349179423.1648.44.camel@vkoul-udesk3> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -9.0 (---------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-9.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.55.52.93 listed in list.dnswl.org] -2.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Linux DaVinci Kernel List , Chris Ball , Russell King - ARM Linux , Benoit Cousson , Arnd Bergmann , Linux Documentation List , Tony Lindgren , Linux MMC List , Devicetree Discuss , Mark Brown , Sekhar Nori , Linux Kernel Mailing List , Rob Herring , Grant Likely , Rob Landley , Dan Williams , Linux SPI Devel List , Linux OMAP List , Linux ARM Kernel List X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Mon, 2012-10-01 at 12:39 -0400, Matt Porter wrote: > Anything you can show at this point? ;) I'd be happy to drop the > half-hack > for a real API. If not, I'm going to carry that to v2 atm. This is what I had done sometime back. Feel free to update.... diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 9c02a45..94ae006 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -86,11 +86,11 @@ enum dma_transaction_type { * @DMA_DEV_TO_DEV: Slave mode & From Device to Device */ enum dma_transfer_direction { - DMA_MEM_TO_MEM, - DMA_MEM_TO_DEV, - DMA_DEV_TO_MEM, - DMA_DEV_TO_DEV, - DMA_TRANS_NONE, + DMA_MEM_TO_MEM = 0x01, + DMA_MEM_TO_DEV = 0x02, + DMA_DEV_TO_MEM = 0x04, + DMA_DEV_TO_DEV = 0x08, + DMA_TRANS_NONE = 0x10, }; /** @@ -371,6 +371,41 @@ struct dma_slave_config { unsigned int slave_id; }; +enum dmaengine_apis { + DMAENGINE_MEMCPY = 0x0001, + DMAENGINE_XOR = 0x0002, + DMAENGINE_XOR_VAL = 0x0004, + DMAENGINE_PQ = 0x0008, + DMAENGINE_PQ_VAL = 0x0010, + DMAENGINE_MEMSET = 0x0020, + DMAENGINE_SLAVE = 0x0040, + DMAENGINE_CYCLIC = 0x0080, + DMAENGINE_INTERLEAVED = 0x0100, + DMAENGINE_SG = 0x0200, +}; + +/* struct dmaengine_chan_caps - expose capability of a channel + * Note: each channel can have same or different capabilities + * + * This primarily classifies capabilities into + * a) APIs/ops supported + * b) channel physical capabilities + * + * @ops: or'ed api capability + * @widths: channel widths supported + * @dirn: channel directions supported + * @bursts: bitmask of burst lengths supported + * @mux: configurable slave id or hard wired + * -1 for hard wired, otherwise valid positive slave id (including zero) + */ +struct dmaengine_chan_caps { + enum dmaengine_apis ops; + enum dma_slave_buswidth widths; + enum dma_transfer_direction dirn; + unsigned int dma_bursts; + int mux; +}; + static inline const char *dma_chan_name(struct dma_chan *chan) { return dev_name(&chan->dev->device); @@ -534,6 +569,7 @@ struct dma_tx_state { * struct with auxiliary transfer status information, otherwise the call * will just return a simple status code * @device_issue_pending: push pending transactions to hardware + * @device_channel_caps: return the capablities of channel */ struct dma_device { @@ -602,6 +638,9 @@ struct dma_device { dma_cookie_t cookie, struct dma_tx_state *txstate); void (*device_issue_pending)(struct dma_chan *chan); + + struct dmaengine_chan_caps *(*device_channel_caps)( + struct dma_chan *chan); }; static inline int dmaengine_device_control(struct dma_chan *chan,