From patchwork Wed Oct 3 09:22:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 1540651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 9E3AD3FDAE for ; Wed, 3 Oct 2012 09:25:22 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TJLAY-0007UL-EN; Wed, 03 Oct 2012 09:23:06 +0000 Received: from mail-bk0-f49.google.com ([209.85.214.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TJLAV-0007U7-Gy for linux-arm-kernel@lists.infradead.org; Wed, 03 Oct 2012 09:23:04 +0000 Received: by bkwj4 with SMTP id j4so5594635bkw.36 for ; Wed, 03 Oct 2012 02:23:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=ScEraWnMsL0/dMneNgfox1ppMYAvI3czLPgeoDAXwtU=; b=oOG8ORloizpWio0NL5heln0C9L2xrQYt1WCNOxx0D82Clp3fn8xAxBnUL4RbFUsrVJ 6+uHVFgv2ZZVb4YMoYCsTwVoRo53gCOwScdZ1j+ZMq6cPCPdsNzqRBmhzZgASs9CBSCx epeiWrTrTlgPdzZX/zVE6wmQ75N1xdpZHX7x6GsV/p/T/SuoV6BHGXQWiKx6UmctKbLi Xn5Ae/KE+duYIZ4GWefIl8yEGT7izXlvgCuIPcb3JxQRT09ltyNsalqyfpnFQLTdIc5G zNMoXsX1H0dMV6dRaykvMotfGxVRdONYiBVqogILXagPKW924ZaNxLrG1tXpUOqE/Nlt YdAg== Received: by 10.204.146.19 with SMTP id f19mr282218bkv.4.1349256180145; Wed, 03 Oct 2012 02:23:00 -0700 (PDT) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id m19sm2846202bkm.8.2012.10.03.02.22.58 (version=SSLv3 cipher=OTHER); Wed, 03 Oct 2012 02:22:59 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: proc-v7: Ensure correct instruction set after cpu_reset Date: Wed, 3 Oct 2012 10:22:50 +0100 Message-Id: <1349256170-4367-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQkTYwzG28mQTVG0cntWL2DiMMJRqmMhOBGM4F4PMY+5/pHhyteAJ9yHlhMC81cG9agsIgvi X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nicolas Pitre , Will Deacon , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Because mov pc, never switches instruction set when executed in Thumb code, Thumb-2 kernels will silently execute the target code after cpu_reset as Thumb code, even if the passed code pointer denotes ARM (bit 0 clear). This patch uses bx instead, ensuring the correct instruction set for the target code. Thumb code in the kernel is not supported prior to ARMv7, so other CPUs are not affected. Signed-off-by: Dave Martin Acked-by: Will Deacon Acked-by: Nicolas Pitre --- arch/arm/mm/proc-v7.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2e2b66..ca5b575 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -57,7 +57,7 @@ ENTRY(cpu_v7_reset) THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) mcr p15, 0, r1, c1, c0, 0 @ disable MMU isb - mov pc, r0 + bx r0 ENDPROC(cpu_v7_reset) .popsection