From patchwork Thu Oct 4 01:26:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 1544321 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 3D33D3FD9C for ; Thu, 4 Oct 2012 01:28:50 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TJaDB-0006HG-Jo; Thu, 04 Oct 2012 01:26:50 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TJaCx-0006FN-GS for linux-arm-kernel@lists.infradead.org; Thu, 04 Oct 2012 01:26:36 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q941QY6d002260; Wed, 3 Oct 2012 20:26:34 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q941QY3i024903; Wed, 3 Oct 2012 20:26:34 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Wed, 3 Oct 2012 20:26:33 -0500 Received: from nucleus.nsc.com (nucleus.nsc.com [10.188.36.112]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q941QWfV015948; Wed, 3 Oct 2012 20:26:33 -0500 From: Mike Turquette To: , Subject: [PATCH 2/7] ARM: omap: add ABB PRM_IRQSTATUS handlers Date: Wed, 3 Oct 2012 18:26:09 -0700 Message-ID: <1349313974-5473-3-git-send-email-mturquette@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349313974-5473-1-git-send-email-mturquette@ti.com> References: <1349313974-5473-1-git-send-email-mturquette@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -9.0 (---------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-9.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-omap@vger.kernel.org, Mike Turquette , linux-arm-kernel@lists.infradead.org, Mike Turquette X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some PRM_IRQSTATUS registers contain a bit to signal that an ABB LDO transition has completed. These tranxdone bits exist for every instance of an ABB LDO; thus these tranxdone bits are supported on 36xx variants for the MPU voltage domain, and on 44xx variants for the MPU and IVA voltage domains. This patch introduces some data structures and helper functions for checking on and clearing the TRANXDONE bits. They are a copy-paste of existing VP functions of similar nature and will be used in forthcoming patches that control the ABB programming sequence during a DVFS transition. Some previous discussion on the design of the ABB PRM handlers can be found here: http://article.gmane.org/gmane.linux.ports.arm.omap/63609 Signed-off-by: Mike Turquette Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/prm2xxx_3xxx.c | 36 +++++++++++++++++++++++++++++ arch/arm/mach-omap2/prm2xxx_3xxx.h | 4 ++++ arch/arm/mach-omap2/prm44xx.c | 44 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/prm44xx.h | 4 ++++ 4 files changed, 88 insertions(+) diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index a0309de..8d3c63f 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -364,3 +364,39 @@ static int __init omap3xxx_prcm_init(void) return ret; } subsys_initcall(omap3xxx_prcm_init); + +/* PRM ABB */ + +/* + * struct omap36xx_abb - OMAP3 ABB register access description + * @tranxdone_status: ABB_xxx_DONE_ST bitmask in PRM_IRQSTATUS reg + */ +struct omap36xx_abb { + u32 tranxdone_status; +}; + +static struct omap36xx_abb omap36xx_abb[] = { + [OMAP3_VP_VDD_MPU_ID] = { + .tranxdone_status = OMAP3630_ABB_LDO_TRANXDONE_ST_MASK, + }, +}; + +#define MAX_ABB_ID ARRAY_SIZE(omap36xx_abb); + +u32 omap3_prm_abb_check_txdone(u8 abb_id) +{ + struct omap36xx_abb *abb = &omap36xx_abb[abb_id]; + u32 irqstatus; + + irqstatus = omap2_prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + return irqstatus & abb->tranxdone_status; +} + +void omap3_prm_abb_clear_txdone(u8 abb_id) +{ + struct omap36xx_abb *abb = &omap36xx_abb[abb_id]; + + omap2_prm_write_mod_reg(abb->tranxdone_status, + OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); +} diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index c9eea9a..c24c039 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -249,6 +249,10 @@ extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); u32 omap3_prm_vp_check_txdone(u8 vp_id); void omap3_prm_vp_clear_txdone(u8 vp_id); +/* OMAP36xx-specific ABB functions */ +u32 omap3_prm_abb_check_txdone(u8 vp_id); +void omap3_prm_abb_clear_txdone(u8 vp_id); + /* * OMAP3 access functions for voltage controller (VC) and * voltage proccessor (VP) in the PRM. diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index bb727c2..9b820d4 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -301,3 +301,47 @@ static int __init omap4xxx_prcm_init(void) return 0; } subsys_initcall(omap4xxx_prcm_init); + +/* PRM ABB */ + +/* + * struct omap4_vp - OMAP4 VP register access description. + * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP + * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg + */ +struct omap4_abb { + u32 irqstatus_mpu; + u32 tranxdone_status; +}; + +static struct omap4_abb omap4_abb[] = { + [OMAP4_VP_VDD_MPU_ID] = { + .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, + .tranxdone_status = OMAP4430_ABB_MPU_DONE_ST_MASK, + }, + [OMAP4_VP_VDD_IVA_ID] = { + .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, + .tranxdone_status = OMAP4430_ABB_IVA_DONE_ST_MASK, + }, +}; + +u32 omap4_prm_abb_check_txdone(u8 abb_id) +{ + struct omap4_abb *abb = &omap4_abb[abb_id]; + u32 irqstatus; + + irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + OMAP4430_PRM_OCP_SOCKET_INST, + abb->irqstatus_mpu); + return irqstatus & abb->tranxdone_status; +} + +void omap4_prm_abb_clear_txdone(u8 abb_id) +{ + struct omap4_abb *abb = &omap4_abb[abb_id]; + + omap4_prminst_write_inst_reg(abb->tranxdone_status, + OMAP4430_PRM_PARTITION, + OMAP4430_PRM_OCP_SOCKET_INST, + abb->irqstatus_mpu); +}; diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index ee72ae6..6a0a00c 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -755,6 +755,10 @@ extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); u32 omap4_prm_vp_check_txdone(u8 vp_id); void omap4_prm_vp_clear_txdone(u8 vp_id); +/* OMAP4-specific ABB functions */ +u32 omap4_prm_abb_check_txdone(u8 abb_id); +void omap4_prm_abb_clear_txdone(u8 abb_id); + /* * OMAP4 access functions for voltage controller (VC) and * voltage proccessor (VP) in the PRM.