From patchwork Wed Oct 10 15:45:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 1574851 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 5438A3FE36 for ; Wed, 10 Oct 2012 15:48:46 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TLyUG-0005AA-H0; Wed, 10 Oct 2012 15:46:21 +0000 Received: from smtp18.mail.ru ([94.100.176.155]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TLyTn-000500-0C for linux-arm-kernel@lists.infradead.org; Wed, 10 Oct 2012 15:45:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=OpN4cZ+KQNqQv1JWNXBnljRPBMAc4Xl7xm4O+AU3GTQ=; b=KCByVVECB2CA46T3mgwcAp8blefNknZ+NqOjYtKJ/GVtnnuQoIJnfOh+xEZ7zt0F/cZpYRB3B/W2miE4bwKUyIHpOQCx3AO3Ew9AcuzEqX3daV9vzPr7uyApH+OcFwZH; Received: from [188.134.40.128] (port=51989 helo=shc.zet) by smtp18.mail.ru with esmtpa (envelope-from ) id 1TLyTl-0007oS-La; Wed, 10 Oct 2012 19:45:49 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/7] ARM: clps711x: rework IRQ sybsustem initialization Date: Wed, 10 Oct 2012 19:45:29 +0400 Message-Id: <1349883933-8881-3-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.7.8.6 In-Reply-To: <1349883933-8881-1-git-send-email-shc_work@mail.ru> References: <1349883933-8881-1-git-send-email-shc_work@mail.ru> X-Spam: Not detected X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [94.100.176.155 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (shc_work[at]mail.ru) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Olof Johansson , Russell King , Alexander Shiyan , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Reworked IRQ subsystem to be able to use some interrupts with "End of interrupt" handler. Signed-off-by: Alexander Shiyan --- arch/arm/mach-clps711x/common.c | 91 +++++++++++++++++++--------- arch/arm/mach-clps711x/include/mach/irqs.h | 4 - 2 files changed, 62 insertions(+), 33 deletions(-) diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 218684f..38a18ee 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -66,6 +66,10 @@ static void int1_mask(struct irq_data *d) static void int1_ack(struct irq_data *d) { +} + +static void int1_eoi(struct irq_data *d) +{ switch (d->irq) { case IRQ_CSINT: clps_writel(0, COEOI); break; case IRQ_TC1OI: clps_writel(0, TC1EOI); break; @@ -86,7 +90,9 @@ static void int1_unmask(struct irq_data *d) } static struct irq_chip int1_chip = { + .name = "Interrupt Vector 1 ", .irq_ack = int1_ack, + .irq_eoi = int1_eoi, .irq_mask = int1_mask, .irq_unmask = int1_unmask, }; @@ -102,6 +108,10 @@ static void int2_mask(struct irq_data *d) static void int2_ack(struct irq_data *d) { +} + +static void int2_eoi(struct irq_data *d) +{ switch (d->irq) { case IRQ_KBDINT: clps_writel(0, KBDEOI); break; } @@ -117,45 +127,68 @@ static void int2_unmask(struct irq_data *d) } static struct irq_chip int2_chip = { + .name = "Interrupt Vector 2 ", .irq_ack = int2_ack, + .irq_eoi = int2_eoi, .irq_mask = int2_mask, .irq_unmask = int2_unmask, }; +struct clps711x_irqdesc { + int nr; + struct irq_chip *chip; + irq_flow_handler_t handle; +}; + +static struct clps711x_irqdesc clps711x_irqdescs[] __initdata = { + { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, }, + { IRQ_EINT1, &int1_chip, handle_level_irq, }, + { IRQ_EINT2, &int1_chip, handle_level_irq, }, + { IRQ_EINT3, &int1_chip, handle_level_irq, }, + { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, }, + { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, }, + { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, }, + { IRQ_TINT, &int1_chip, handle_fasteoi_irq, }, + { IRQ_UTXINT1, &int1_chip, handle_level_irq, }, + { IRQ_URXINT1, &int1_chip, handle_level_irq, }, + { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, }, + { IRQ_SSEOTI, &int1_chip, handle_level_irq, }, + { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, }, + { IRQ_SS2RX, &int2_chip, handle_level_irq, }, + { IRQ_SS2TX, &int2_chip, handle_level_irq, }, + { IRQ_UTXINT2, &int2_chip, handle_level_irq, }, + { IRQ_URXINT2, &int2_chip, handle_level_irq, }, +}; + void __init clps711x_init_irq(void) { unsigned int i; - for (i = 0; i < NR_IRQS; i++) { - if (INT1_IRQS & (1 << i)) { - irq_set_chip_and_handler(i, &int1_chip, - handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - if (INT2_IRQS & (1 << i)) { - irq_set_chip_and_handler(i, &int2_chip, - handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } + /* Disable interrupts */ + clps_writel(0, INTMR1); + clps_writel(0, INTMR2); + clps_writel(0, INTMR3); + + /* Clear down any pending interrupts */ + clps_writel(0, BLEOI); + clps_writel(0, MCEOI); + clps_writel(0, COEOI); + clps_writel(0, TC1EOI); + clps_writel(0, TC2EOI); + clps_writel(0, RTCEOI); + clps_writel(0, TEOI); + clps_writel(0, UMSEOI); + clps_writel(0, KBDEOI); + clps_writel(0, SRXEOF); + clps_writel(0xffffffff, DAISR); + + for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) { + irq_set_chip_and_handler(clps711x_irqdescs[i].nr, + clps711x_irqdescs[i].chip, + clps711x_irqdescs[i].handle); + set_irq_flags(clps711x_irqdescs[i].nr, + IRQF_VALID | IRQF_PROBE); } - - /* - * Disable interrupts - */ - clps_writel(0, INTMR1); - clps_writel(0, INTMR2); - - /* - * Clear down any pending interrupts - */ - clps_writel(0, COEOI); - clps_writel(0, TC1EOI); - clps_writel(0, TC2EOI); - clps_writel(0, RTCEOI); - clps_writel(0, TEOI); - clps_writel(0, UMSEOI); - clps_writel(0, SYNCIO); - clps_writel(0, KBDEOI); } static void clps711x_clockevent_set_mode(enum clock_event_mode mode, diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h index 14d215f..1ea56db 100644 --- a/arch/arm/mach-clps711x/include/mach/irqs.h +++ b/arch/arm/mach-clps711x/include/mach/irqs.h @@ -34,8 +34,6 @@ #define IRQ_UMSINT 14 #define IRQ_SSEOTI 15 -#define INT1_IRQS (0x0000fff0) - /* * Interrupts from INTSR2 */ @@ -45,6 +43,4 @@ #define IRQ_UTXINT2 (16+12) /* bit 12 */ #define IRQ_URXINT2 (16+13) /* bit 13 */ -#define INT2_IRQS (0x30070000) - #define NR_IRQS 30