From patchwork Mon Oct 15 08:48:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 1592871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 658AB3FD86 for ; Mon, 15 Oct 2012 08:50:25 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TNgLW-0001Wl-Dh; Mon, 15 Oct 2012 08:48:22 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TNgLT-0001WX-84 for linux-arm-kernel@lists.infradead.org; Mon, 15 Oct 2012 08:48:20 +0000 Received: by mail-pa0-f49.google.com with SMTP id bi5so4862304pad.36 for ; Mon, 15 Oct 2012 01:48:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=QcZhBvtLHfjee1FONiInnbgHERyP18JdrMoes6tMGw8=; b=JAfzDwtQCEFZvNLl3SMUYRPBygPBqFO505re5/fRcaketmEw9BhcNOdN0e3HeNPvch pDG1wCpwgEbY6Ew2kMknZlr642fHaBpi84siTYCDHUwHx8pj6DSeftgxGYvWiFoUXsWE /t1XJE/fZ6HSo6WDG5NLUZHZQQXcXjwTdiltOYn+M+F+XkE0Bq8VwS223Wc4pD5YEcJO bphjaBwTYaf+ohg4fvbXRzs/FbP1iqS+zu2Oubzo0iV24/1xaTci4UK1QQHUHUZZfWFT pYMvCpv1hVIWH7KRB+FbzxledKu5Ud1WGoWZ5vyQ5WLcYEZohQd0w2sXxhvMyZZ4oFaU GQzw== Received: by 10.68.203.228 with SMTP id kt4mr35172246pbc.87.1350290897619; Mon, 15 Oct 2012 01:48:17 -0700 (PDT) Received: from S2101-09.ap.freescale.net ([117.81.35.66]) by mx.google.com with ESMTPS id op7sm8748492pbc.52.2012.10.15.01.48.12 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 01:48:16 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: dts: imx6q-arm2: move NANDF_CS pins out of 'hog' Date: Mon, 15 Oct 2012 16:48:04 +0800 Message-Id: <1350290884-26594-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmnFA/SPldz7kObvg/KLKmVDTYDd74WcEtH+l8TIzo/4LoOCS2knH3TyQiX27ImSaDMGZZ5 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Huang Shijie , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Commit 9e3c0066 (ARM: dts: imx6q-arm2: add pinctrl for uart and enet) defines NANDF_CS pins as gpio in 'hog', assuming these two pins are always used by usdhc3 in gpio mode as card-detection and write-protection on ARM2 board. But it's not true. These pins are shared by usdhc3 and gpmi-nand. We should have the pins functional for gpmi-nand when usdhc3 is disabled. Move the pins out of 'hog', so that pins only work in gpio mode as CD and WP when usdhc3 is enabled, and otherwise they are available for gpmi-nand. Reported-by: Huang Shijie Signed-off-by: Shawn Guo Tested-by: Huang Shijie --- Huang, Please help test the patch to see if it fixes your problem, thanks. Shawn arch/arm/boot/dts/imx6q-arm2.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 15df4c1..5bfa02a 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -37,6 +37,13 @@ pinctrl_hog: hoggrp { fsl,pins = < 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ + >; + }; + }; + + arm2 { + pinctrl_usdhc3_arm2: usdhc3grp-arm2 { + fsl,pins = < 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ >; @@ -58,7 +65,8 @@ wp-gpios = <&gpio6 14 0>; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-0 = <&pinctrl_usdhc3_1 + &pinctrl_usdhc3_arm2>; status = "okay"; };