From patchwork Thu Oct 25 10:58:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Hecht X-Patchwork-Id: 1643171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 9B97DDF2AB for ; Thu, 25 Oct 2012 11:00:39 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TRL9K-0001H4-LA; Thu, 25 Oct 2012 10:58:54 +0000 Received: from mail-bk0-f49.google.com ([209.85.214.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TRL91-0001Cz-3L for linux-arm-kernel@lists.infradead.org; Thu, 25 Oct 2012 10:58:38 +0000 Received: by mail-bk0-f49.google.com with SMTP id j4so585051bkw.36 for ; Thu, 25 Oct 2012 03:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=9NqmnaDjgrOWIG3DGcjm3gpKZD1uAQLFZVnczoRsZeQ=; b=l8vcFkWATUMql4FXb3+RSKC1gxp3QikZvQgeShCO/Qdam5+KfitZES3rTZrgfNxp4y kT5IShMKdLusbxR6PexAQnQcb4F6owekxIV5VrvCooU+9eSkr+X+vvxEadVT33DLseJx YQ+ndRoEASTVrWUWAjwd5Ib/YBIWUnlTfY5p056E1eTrLzRm4lpccAFnie2hBM1Ki7uW NzpNuDTuqlxMHzMwmhj/gEfcI46Hzl+Rfn681tOWNiazX2eK1JrwcPE772pcinv5TxY1 gIWiCjf1thecBxPcMu3i0a8/6UR53HoDSZheJCC3VFj/yh9jbKSk93sniMmJeNb/A0id QVfA== Received: by 10.204.131.89 with SMTP id w25mr5740487bks.35.1351162713928; Thu, 25 Oct 2012 03:58:33 -0700 (PDT) Received: from localhost.localdomain (p54932E5B.dip.t-dialin.net. [84.147.46.91]) by mx.google.com with ESMTPS id j24sm9781113bkv.0.2012.10.25.03.58.32 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 03:58:33 -0700 (PDT) From: Bastian Hecht To: linux-sh@vger.kernel.org Subject: [PATCH 3/3] ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with scu_power_mode Date: Thu, 25 Oct 2012 12:58:22 +0200 Message-Id: <1351162702-8391-4-git-send-email-hechtb@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1351162702-8391-1-git-send-email-hechtb@gmail.com> References: <1351162702-8391-1-git-send-email-hechtb@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.7 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (hechtb[at]googlemail.com) 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.9 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Cc: Simon Horman , Magnus Damm , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org We can remove the extra code of modify_scu_cpu_psr() and use the cleaner generic ARM helper scu_power_mode(). As every CPU only deals with its own power register and scu_power_mode() operates with 8-bit accesses, we save the locking overhead too. Signed-off-by: Bastian Hecht --- arch/arm/mach-shmobile/smp-r8a7779.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 2ce6af9..9def0f2 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -61,9 +61,6 @@ static void __iomem *scu_base_addr(void) return (void __iomem *)0xf0000000; } -static DEFINE_SPINLOCK(scu_lock); -static unsigned long tmp; - #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); @@ -73,20 +70,6 @@ void __init r8a7779_register_twd(void) } #endif -static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) -{ - void __iomem *scu_base = scu_base_addr(); - - spin_lock(&scu_lock); - tmp = __raw_readl(scu_base + 8); - tmp &= ~clr; - tmp |= set; - spin_unlock(&scu_lock); - - /* disable cache coherency after releasing the lock */ - __raw_writel(tmp, scu_base + 8); -} - static unsigned int __init r8a7779_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); @@ -102,7 +85,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) cpu = cpu_logical_map(cpu); /* disable cache coherency */ - modify_scu_cpu_psr(3 << (cpu * 8), 0); + scu_power_mode(scu_base_addr(), 3); if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -145,7 +128,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct cpu = cpu_logical_map(cpu); /* enable cache coherency */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); + scu_power_mode(scu_base_addr(), 0); if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -158,15 +141,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { - int cpu = cpu_logical_map(0); - scu_enable(scu_base_addr()); /* Map the reset vector (in headsmp.S) */ __raw_writel(__pa(shmobile_secondary_vector), AVECR); /* enable cache coherency on CPU0 */ - modify_scu_cpu_psr(0, 3 << (cpu * 8)); + scu_power_mode(scu_base_addr(), 0); r8a7779_pm_init();