From patchwork Thu Oct 25 16:11:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 1645711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id ABAA03FE1C for ; Thu, 25 Oct 2012 16:16:17 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TRQ4E-0000S4-4s; Thu, 25 Oct 2012 16:13:58 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TRQ2Z-0008Nr-67 for linux-arm-kernel@lists.infradead.org; Thu, 25 Oct 2012 16:12:25 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9PGC3aY031034; Thu, 25 Oct 2012 11:12:03 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9PGC2fN015826; Thu, 25 Oct 2012 11:12:02 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Thu, 25 Oct 2012 11:12:01 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9PGC1jv005704; Thu, 25 Oct 2012 11:12:01 -0500 Received: from a0868495 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1TRQ2L-00036x-Bv; Thu, 25 Oct 2012 12:12:01 -0400 From: Murali Karicheri To: , , , , , , , , , , , , , Subject: [PATCH v3 09/11] ARM: davinci - dm644x: update SoC code to remove the clock data Date: Thu, 25 Oct 2012 12:11:55 -0400 Message-ID: <1351181518-11882-10-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351181518-11882-1-git-send-email-m-karicheri2@ti.com> References: <1351181518-11882-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.41 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Murali Karicheri , linux-keystone@list.ti.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org As part of the migration, the clock data is now moved to the driver/clk/ davinci/dm644x-clock.c. Currently the clock data is placed under ifndef CONFIG_COMMON_CLK directive and will be removed in a subsequent patch. Signed-off-by: Murali Karicheri --- arch/arm/mach-davinci/davinci.h | 3 +++ arch/arm/mach-davinci/dm644x.c | 28 ++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 8661b20..ae9b1af 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -100,4 +100,7 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); void dm646x_setup_vpif(struct vpif_display_config *, struct vpif_capture_config *); + +extern void __init dm644x_clk_init(void); + #endif /*__DAVINCI_H */ diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 0755d46..bf64b75 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -9,7 +9,9 @@ * or implied. */ #include +#ifndef CONFIG_COMMON_CLK #include +#endif #include #include @@ -18,7 +20,9 @@ #include #include #include +#ifndef CONFIG_COMMON_CLK #include +#endif #include #include #include @@ -26,14 +30,11 @@ #include #include "davinci.h" -#include "clock.h" #include "mux.h" #include "asp.h" - -/* - * Device specific clocks - */ -#define DM644X_REF_FREQ 27000000 +#ifndef CONFIG_COMMON_CLK +#include "clock.h" +#endif #define DM644X_EMAC_BASE 0x01c80000 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) @@ -42,6 +43,12 @@ #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 +#ifndef CONFIG_COMMON_CLK +/* + * Device specific clocks + */ +#define DM644X_REF_FREQ 27000000 + static struct pll_data pll1_data = { .num = 1, .phys_base = DAVINCI_PLL1_BASE, @@ -324,6 +331,7 @@ static struct clk_lookup dm644x_clks[] = { CLK("watchdog", NULL, &timer2_clk), CLK(NULL, NULL, NULL), }; +#endif static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, @@ -821,7 +829,9 @@ static struct davinci_id dm644x_ids[] = { }, }; +#ifndef CONFIG_COMMON_CLK static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; +#endif /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers @@ -879,9 +889,13 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .jtag_id_reg = 0x01c40028, .ids = dm644x_ids, .ids_num = ARRAY_SIZE(dm644x_ids), +#ifdef CONFIG_COMMON_CLK + .clk_init = dm644x_clk_init, +#else .cpu_clks = dm644x_clks, .psc_bases = dm644x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), +#endif .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm644x_pins, .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), @@ -923,11 +937,13 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, dm644x_vpfe_dev.dev.platform_data = vpfe_cfg; platform_device_register(&dm644x_ccdc_dev); platform_device_register(&dm644x_vpfe_dev); +#ifndef CONFIG_COMMON_CLK /* Add ccdc clock aliases */ clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); +#endif } if (vpbe_cfg) {