From patchwork Tue Oct 30 16:01:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasanth Ananthan X-Patchwork-Id: 1670751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 4E36BDFB7B for ; Tue, 30 Oct 2012 16:05:18 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TTEH9-0000ng-8F; Tue, 30 Oct 2012 16:02:47 +0000 Received: from mail-bk0-f49.google.com ([209.85.214.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TTEGT-0000b3-F2 for linux-arm-kernel@lists.infradead.org; Tue, 30 Oct 2012 16:02:07 +0000 Received: by mail-bk0-f49.google.com with SMTP id j4so245840bkw.36 for ; Tue, 30 Oct 2012 09:02:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=AnGqKwSCc2mwnZjBi7uxZa5Pm1RQWV8/NwM5FtbRBYQ=; b=R9npCdJaSEXe12kFX7yOG7m3JH53uJti4YADG+etFzfNTr5H+UU+GvVeP+lMYxQlh8 8icJqq+nplkBoiWnCb6gCsbgRvP9oOjK89DVTKh8Ixzf+ZHkeeDmoZLkyj4rRVaSQEKt ytiMda+YKtCMZPAwYncINueiTUfXpNgzUD8nEz35/SEVVzmR3yqk06ztEIbK5k3cdg3T JTqsVr3Qoxf2GluZZ7WtUHSzgarY5c656b8d0SgmBgrvbV8QICAaORX5sjwv0xQ62A+k PCNZvtXhigl3dEZrdXbc547k+wP8zaMRgIv8IpblzABsNlg+/vXduC/qTWdxGVc3LKqo kRhQ== Received: by 10.204.9.9 with SMTP id j9mr10526530bkj.12.1351612924992; Tue, 30 Oct 2012 09:02:04 -0700 (PDT) Received: from localhost.localdomain ([91.224.175.20]) by mx.google.com with ESMTPS id v14sm1522974bkv.10.2012.10.30.09.02.03 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 30 Oct 2012 09:02:04 -0700 (PDT) From: Vasanth Ananthan To: kgene.kim@samsung.com, jgarzik@pobox.com, linux@arm.linux.org.uk Subject: [PATCH v2 5/6] DRIVERS: ATA: SATA controller driver Date: Tue, 30 Oct 2012 17:01:36 +0100 Message-Id: <1351612897-14923-6-git-send-email-vasanthananthan@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1351612897-14923-1-git-send-email-vasanthananthan@gmail.com> References: <1351612897-14923-1-git-send-email-vasanthananthan@gmail.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (vasanthananthan[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: linux-samsung-soc@vger.kernel.org, Vasanth Ananthan , linux-ide@vger.kernel.org, thomas.abraham@linaro.org, Vasanth Ananthan , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds a platform driver for SATA controller. Signed-off-by: Vasanth Ananthan --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 3 + drivers/ata/Kconfig | 12 ++ drivers/ata/Makefile | 1 + drivers/ata/sata_exynos.c | 268 ++++++++++++++++++++++++++ 4 files changed, 284 insertions(+), 0 deletions(-) create mode 100644 drivers/ata/sata_exynos.c diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index d4e392b..3716ce8 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -367,4 +367,7 @@ #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) +/* Only for EXYNOS5250 */ +#define EXYNOS5_SATA_PHY_CONTROL S5P_PMUREG(0x0724) + #endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index e3a2972..f3384ed 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -93,6 +93,18 @@ config SATA_PHY with the framework through the APIs provided and the SATA device finds and requests for an appropriate PHY device. +config SATA_EXYNOS + bool "Exynos SATA AHCI support" + select I2C + select HAVE_S3C2410_I2C + select I2C_S3C2410 + select SATA_PHY + help + This option enables support for Exynos AHCI Serial ATA + controllers. + + If unsure, say N. + config SATA_FSL tristate "Freescale 3.0Gbps SATA support" depends on FSL_SOC diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 3d219a9..43bb38e 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o obj-$(CONFIG_SATA_PHY) += sata_phy.o +obj-$(CONFIG_SATA_EXYNOS) += sata_exynos.o libahci.o # SFF w/ custom DMA obj-$(CONFIG_PDC_ADMA) += pdc_adma.o diff --git a/drivers/ata/sata_exynos.c b/drivers/ata/sata_exynos.c new file mode 100644 index 0000000..41dc17d --- /dev/null +++ b/drivers/ata/sata_exynos.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - SATA controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ahci.h" +#include "sata_phy.h" + +#define MHZ (1000 * 1000) + +static const struct ata_port_info ahci_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, +}; + +static struct scsi_host_template ahci_platform_sht = { + AHCI_SHT("ahci_platform"), +}; + +struct exynos_sata { + struct clk *sclk; + struct clk *clk; + struct sata_phy *phy; + int irq; + unsigned int freq; +}; + +static void exynos_sata_parse_dt(struct device_node *np, + struct exynos_sata *sata) +{ + if (!np) + return; + + of_property_read_u32(np, "samsung,sata-freq", &sata->freq); +} + +static int __init exynos_sata_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_port_info pi = ahci_port_info; + const struct ata_port_info *ppi[] = { &pi, NULL }; + struct ahci_host_priv *hpriv; + struct exynos_sata *sata; + struct ata_host *host; + struct resource *mem; + int n_ports, i, ret; + + sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL); + if (!sata) { + dev_err(dev, "can't alloc sata\n"); + return -EINVAL; + } + + hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); + if (!hpriv) { + dev_err(dev, "can't alloc ahci_host_priv\n"); + ret = -ENOMEM; + goto err1; + } + + hpriv->flags |= (unsigned long)pi.private_data; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "no mmio space\n"); + ret = -EINVAL; + goto err2; + } + + sata->irq = platform_get_irq(pdev, 0); + if (sata->irq <= 0) { + dev_err(dev, "no irq\n"); + ret = -EINVAL; + goto err2; + } + + hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); + if (!hpriv->mmio) { + dev_err(dev, "can't map %pR\n", mem); + ret = -ENOMEM; + goto err2; + } + + exynos_sata_parse_dt(dev->of_node, sata); + + sata->sclk = devm_clk_get(dev, "sclk_sata"); + if (IS_ERR(sata->sclk)) { + dev_err(dev, "failed to get sclk_sata\n"); + ret = PTR_ERR(sata->sclk); + goto err3; + } + clk_enable(sata->sclk); + + clk_set_rate(sata->sclk, sata->freq * MHZ); + + sata->clk = devm_clk_get(dev, "sata"); + if (IS_ERR(sata->clk)) { + dev_err(dev, "failed to get sata clock\n"); + ret = PTR_ERR(sata->clk); + goto err4; + } + clk_enable(sata->clk); + + /* Get a gen 3 PHY controller */ + + sata->phy = sata_get_phy(SATA_PHY_GENERATION3); + if (!sata->phy) { + dev_err(dev, "failed to get sata phy\n"); + ret = -EPROBE_DEFER; + goto err5; + } + + /* Initialize the controller */ + + ret = sata_init_phy(sata->phy); + if (ret < 0) { + dev_err(dev, "failed to initialize sata phy\n"); + goto err6; + } + + ahci_save_initial_config(dev, hpriv, 0, 0); + + /* prepare host */ + if (hpriv->cap & HOST_CAP_NCQ) + pi.flags |= ATA_FLAG_NCQ; + + if (hpriv->cap & HOST_CAP_PMP) + pi.flags |= ATA_FLAG_PMP; + + ahci_set_em_messages(hpriv, &pi); + + /* CAP.NP sometimes indicate the index of the last enabled + * port, at other times, that of the last possible port, so + * determining the maximum port number requires looking at + * both CAP.NP and port_map. + */ + n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); + + host = ata_host_alloc_pinfo(dev, ppi, n_ports); + if (!host) { + ret = -ENOMEM; + goto err7; + } + + host->private_data = hpriv; + + if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) + host->flags |= ATA_HOST_PARALLEL_SCAN; + else + pr_info(KERN_INFO + "ahci: SSS flag set, parallel bus scan disabled\n"); + + if (pi.flags & ATA_FLAG_EM) + ahci_reset_em(host); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + + ata_port_desc(ap, "mmio %pR", mem); + ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); + + /* set enclosure management message type */ + if (ap->flags & ATA_FLAG_EM) + ap->em_message_type = hpriv->em_msg_type; + + /* disabled/not-implemented port */ + if (!(hpriv->port_map & (1 << i))) + ap->ops = &ata_dummy_port_ops; + } + + ret = ahci_reset_controller(host); + if (ret) + goto err7; + + ahci_init_controller(host); + ahci_print_info(host, "platform"); + + ret = ata_host_activate(host, sata->irq, ahci_interrupt, IRQF_SHARED, + &ahci_platform_sht); + if (ret) + goto err7; + + platform_set_drvdata(pdev, sata); + + return 0; + + err7: + sata_shutdown_phy(sata->phy); + + err6: + sata_put_phy(sata->phy); + + err5: + clk_disable(sata->clk); + devm_clk_put(dev, sata->clk); + + err4: + clk_disable(sata->sclk); + devm_clk_put(dev, sata->sclk); + + err3: + devm_iounmap(dev, hpriv->mmio); + + err2: + devm_kfree(dev, hpriv); + + err1: + devm_kfree(dev, sata); + + return ret; +} + +static int __devexit exynos_sata_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_host *host = dev_get_drvdata(dev); + struct exynos_sata *sata = platform_get_drvdata(pdev); + + ata_host_detach(host); + + sata_shutdown_phy(sata->phy); + sata_put_phy(sata->phy); + + return 0; +} + +static const struct of_device_id ahci_of_match[] = { + { .compatible = "samsung,exynos5-sata-ahci", }, +}; + +MODULE_DEVICE_TABLE(of, ahci_of_match); + +static struct platform_driver exynos_sata_driver = { + .probe = exynos_sata_probe, + .remove = exynos_sata_remove, + .driver = { + .name = "ahci-sata", + .owner = THIS_MODULE, + .of_match_table = ahci_of_match, + }, +}; + +module_platform_driver(exynos_sata_driver); + +MODULE_DESCRIPTION("EXYNOS SATA DRIVER"); +MODULE_AUTHOR("Vasanth Ananthan, "); +MODULE_LICENSE("GPL");