From patchwork Wed Oct 31 09:02:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 1676711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id CCC6BDF2F6 for ; Wed, 31 Oct 2012 09:07:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TTUF9-00052L-36; Wed, 31 Oct 2012 09:05:47 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TTUEL-0004oY-Ad for linux-arm-kernel@lists.infradead.org; Wed, 31 Oct 2012 09:04:58 +0000 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 31 Oct 2012 02:04:19 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Wed, 31 Oct 2012 02:04:49 -0700 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Wed, 31 Oct 2012 02:04:49 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Wed, 31 Oct 2012 02:04:49 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Wed, 31 Oct 2012 02:04:49 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q9V94bq8003269; Wed, 31 Oct 2012 02:04:47 -0700 (PDT) From: Laxman Dewangan To: , Subject: [PATCH V4 4/4] ARM: tegra: config: enable spi driver for Tegra SLINK controller Date: Wed, 31 Oct 2012 14:32:55 +0530 Message-ID: <1351674176-20603-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1351674176-20603-1-git-send-email-ldewangan@nvidia.com> References: <1351674176-20603-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121031_050457_574984_FA4D04BE X-CRM114-Status: GOOD ( 10.59 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, Laxman Dewangan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Also enable the MTD, MTD_M25P80 and MTD_CHAR driver to enable SPI flash. Signed-off-by: Laxman Dewangan --- No change from V1 and V2. Changes from V2: - enable MTD, MTD_M25P80 and MTD_CHAR drivers. arch/arm/configs/tegra_defconfig | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index fb29680..9dac09b 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -80,6 +80,9 @@ CONFIG_RFKILL_GPIO=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_AD525X_DPOT=y @@ -117,7 +120,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_TEGRA=y CONFIG_SPI=y -CONFIG_SPI_TEGRA=y +CONFIG_SPI_TEGRA20_SLINK=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y