From patchwork Wed Oct 31 23:04:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1682291 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 053824005F for ; Wed, 31 Oct 2012 23:08:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TThLC-00005h-CE; Wed, 31 Oct 2012 23:04:54 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TThKn-0008R8-Ml for linux-arm-kernel@lists.infradead.org; Wed, 31 Oct 2012 23:04:32 +0000 Received: by mail-pa0-f49.google.com with SMTP id bi5so1206565pad.36 for ; Wed, 31 Oct 2012 16:04:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=QA67K5S8o2QhyUBESzoPfYdDd+cvscmr98cIhfnp3FI=; b=FstMVsC+iz0aToPg0w4GTTrEvqp+PiLgqo5LodEg9dMuYwBgCRyEIbD9rAuAAQ0kah BQB7fJVnYIxOfdjyXqKhRmbKxjW8VrDE01Zv73n7nUiPpkB0mYJFFQmZBiY3udwKzBwN Linlzf+sQGdTgg8ia3Qx00sfDpNoiQu/iHu1oKpR2i1Fc+AFZBixReLgJSJOQWGWU9sx xHZQMtDgXtHpCJgfEnpHXhD3UdiwOHgnIkQKpm5eiUojX/bG1KiHMEk08Sl632wYYPi/ 7PjH2z8oVJQq77mYRPzw8lfsXDSfnGaXFXFNHOgJSNngvz/5tScjgCBXgQ0zHPqP1qDt sk2Q== Received: by 10.68.137.234 with SMTP id ql10mr55337341pbb.158.1351724669349; Wed, 31 Oct 2012 16:04:29 -0700 (PDT) Received: from localhost ([61.172.13.185]) by mx.google.com with ESMTPS id iq3sm2961221pbc.5.2012.10.31.16.04.25 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 31 Oct 2012 16:04:28 -0700 (PDT) From: Haojian Zhuang To: swarren@wwwdotorg.org, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, tony@atomide.com, devicetree-discuss@lists.org, linus.walleij@linaro.org Subject: [PATCH v3 2/9] pinctrl: single: support gpio request and free Date: Thu, 1 Nov 2012 07:04:14 +0800 Message-Id: <1351724661-29050-3-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351724661-29050-1-git-send-email-haojian.zhuang@gmail.com> References: <1351724661-29050-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121031_190429_998418_921EBD7B X-CRM114-Status: GOOD ( 21.09 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (haojian.zhuang[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Marvell's PXA/MMP silicon also match the behavior of pinctrl-single. Each pin binds to one register. A lot of pins could be configured as gpio. Now add these properties in below. : include "pinctrl-single,gpio" & "pinctrl,gpio-func" properties. pinctrl-single,gpio: pinctrl-single,gpio-func: pinctrl-single,gpio-ranges: phandle list of gpio range array Signed-off-by: Haojian Zhuang --- drivers/pinctrl/pinctrl-single.c | 100 +++++++++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 726a729..a7c5fdd 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -30,6 +30,7 @@ #define PCS_MUX_BITS_NAME "pinctrl-single,bits" #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) #define PCS_OFF_DISABLED ~0U +#define PCS_MAX_GPIO_VALUES 3 /** * struct pcs_pingroup - pingroups for a function @@ -77,6 +78,18 @@ struct pcs_function { }; /** + * struct pcs_gpio_range - pinctrl gpio range + * @range: subrange of the GPIO number space + * @gpio_func: gpio function value in the pinmux register + * @func_en: need to handle gpio function in the pinmux register + */ +struct pcs_gpio_range { + struct pinctrl_gpio_range range; + int gpio_func; + unsigned func_en:1; +}; + +/** * struct pcs_data - wrapper for data needed by pinctrl framework * @pa: pindesc array * @cur: index to current element @@ -123,8 +136,10 @@ struct pcs_name { * @ftree: function index radix tree * @pingroups: list of pingroups * @functions: list of functions + * @ranges: list of gpio ranges * @ngroups: number of pingroups * @nfuncs: number of functions + * @nranges: number of gpio ranges * @desc: pin controller descriptor * @read: register read function to use * @write: register write function to use @@ -148,8 +163,10 @@ struct pcs_device { struct radix_tree_root ftree; struct list_head pingroups; struct list_head functions; + struct list_head ranges; unsigned ngroups; unsigned nfuncs; + unsigned nranges; struct pinctrl_desc desc; unsigned (*read)(void __iomem *reg); void (*write)(unsigned val, void __iomem *reg); @@ -403,9 +420,27 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, } static int pcs_request_gpio(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset) + struct pinctrl_gpio_range *range, unsigned pin) { - return -ENOTSUPP; + struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); + struct pcs_gpio_range *gpio = NULL; + int end, mux_bytes; + unsigned data; + + gpio = container_of(range, struct pcs_gpio_range, range); + if (!gpio->func_en) + return -ENOTSUPP; + end = range->pin_base + range->npins - 1; + if (pin < range->pin_base || pin > end) { + dev_err(pctldev->dev, "pin %d isn't in the range of " + "%d to %d\n", pin, range->pin_base, end); + return -EINVAL; + } + mux_bytes = pcs->width / BITS_PER_BYTE; + data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; + data |= gpio->gpio_func; + pcs->write(data, pcs->base + pin * mux_bytes); + return 0; } static struct pinmux_ops pcs_pinmux_ops = { @@ -879,6 +914,62 @@ static void pcs_free_resources(struct pcs_device *pcs) static struct of_device_id pcs_of_match[]; +static int __devinit pcs_add_gpio_range(struct device_node *node, + struct pcs_device *pcs) +{ + struct pcs_gpio_range *gpio; + struct device_node *np; + const __be32 *list; + const char list_name[] = "pinctrl-single,gpio-ranges"; + const char name[] = "pinctrl-single"; + u32 gpiores[PCS_MAX_GPIO_VALUES]; + int ret, size, i, mux_bytes = 0; + + list = of_get_property(node, list_name, &size); + if (!list) + return 0; + size = size / sizeof(*list); + for (i = 0; i < size; i++) { + np = of_parse_phandle(node, list_name, i); + memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES); + ret = of_property_read_u32_array(np, "pinctrl-single,gpio", + gpiores, PCS_MAX_GPIO_VALUES); + if (ret < 0) + return -ENOENT; + gpio = devm_kzalloc(pcs->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) { + dev_err(pcs->dev, "failed to allocate pcs gpio\n"); + return -ENOMEM; + } + gpio->range.id = i; + gpio->range.base = gpiores[0]; + gpio->range.npins = gpiores[1]; + gpio->range.name = devm_kzalloc(pcs->dev, sizeof(name), + GFP_KERNEL); + if (!gpio->range.name) { + dev_err(pcs->dev, "failed to allocate range name\n"); + return -ENOMEM; + } + memcpy(&gpio->range.name, name, sizeof(name)); + mux_bytes = pcs->width / BITS_PER_BYTE; + gpio->range.pin_base = gpiores[2] / mux_bytes; + memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES); + ret = of_property_read_u32(np, "pinctrl-single,gpio-func", + &gpio->gpio_func); + if (ret < 0) + return -ENOENT; + gpio->func_en = 1; + + mutex_lock(&pcs->mutex); + list_add_tail(&gpio->range.node, &pcs->ranges); + pcs->nranges++; + mutex_unlock(&pcs->mutex); + + pinctrl_add_gpio_range(pcs->pctl, &gpio->range); + } + return 0; +} + static int __devinit pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -900,6 +991,7 @@ static int __devinit pcs_probe(struct platform_device *pdev) mutex_init(&pcs->mutex); INIT_LIST_HEAD(&pcs->pingroups); INIT_LIST_HEAD(&pcs->functions); + INIT_LIST_HEAD(&pcs->ranges); PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); @@ -975,6 +1067,10 @@ static int __devinit pcs_probe(struct platform_device *pdev) goto free; } + ret = pcs_add_gpio_range(np, pcs); + if (ret < 0) + goto free; + dev_info(pcs->dev, "%i pins at pa %p size %u\n", pcs->desc.npins, pcs->base, pcs->size);