From patchwork Wed Oct 31 23:04:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1682331 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 92118DFB80 for ; Wed, 31 Oct 2012 23:09:51 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TThM1-0000N6-Ra; Wed, 31 Oct 2012 23:05:46 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TThL8-0008R8-L9 for linux-arm-kernel@lists.infradead.org; Wed, 31 Oct 2012 23:04:52 +0000 Received: by mail-pa0-f49.google.com with SMTP id bi5so1206565pad.36 for ; Wed, 31 Oct 2012 16:04:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=DQD/9MbSDFParYV9xDbMR03nNHZgZidmB42BSNMYqiA=; b=cyjlgQeWYjWmQK7OqFpyXr7Ph694bEwHstI3X72RrB6A8HaZj6/TB5rkIKt2i5b+9u 2N3smaW7vcfUHVecNogIo8nZ4h9pySsM5s8wprXAropUpIfO14hKz9g1gytA8Ekn4ogk cCa81dCD+JLzPbkL7tgfhSoxrq8+gAU+ZQW8kJUbYFETJ6VBGWCZvVlm5Bfqofzr2T0e e0OZfqCWWVWJRCL60dXLjhm9wK7CudjgBZrvzKHjbwBgBYiHtlSW6WXVYJF/dJ1HJ08I BS0dxzU/uRpcPuxWwZW19PFHSS6faf+GZmM5ufmzFcsOMz11kaMKQItLyTe3CxqIdTeE pnUg== Received: by 10.66.73.230 with SMTP id o6mr105988552pav.45.1351724690356; Wed, 31 Oct 2012 16:04:50 -0700 (PDT) Received: from localhost ([61.172.13.185]) by mx.google.com with ESMTPS id rg9sm2119159pbc.46.2012.10.31.16.04.47 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 31 Oct 2012 16:04:49 -0700 (PDT) From: Haojian Zhuang To: swarren@wwwdotorg.org, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, tony@atomide.com, devicetree-discuss@lists.org, linus.walleij@linaro.org Subject: [PATCH v3 5/9] document: devicetree: bind pinconf with pin-single Date: Thu, 1 Nov 2012 07:04:17 +0800 Message-Id: <1351724661-29050-6-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351724661-29050-1-git-send-email-haojian.zhuang@gmail.com> References: <1351724661-29050-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121031_190450_905125_CC2AC8BF X-CRM114-Status: GOOD ( 15.09 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (haojian.zhuang[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add comments with pinconf & gpio range in the document of pinctrl-single. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 66 ++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45..15f4dae 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -17,6 +17,41 @@ Optional properties: - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,gpio-ranges : gpio range list of phandles. + Must be present if gpio range phandle is specified. + This property should be existing in .dtsi files for those silicons. + +- pinctrl-single,gpio : array with gpio range start, size & register + offset. Must be present if gpio range phandle is specified. + This property should be existing in .dts files for those boards. + +- pinctrl-single,gpio-func : gpio function value in the pinmux register. + Must be present if gpio range phandle is specified. + This property should be existing in .dts files for those boards. + +- pinctrl-single,power-source-mask : mask of setting power source in + the pinmux register + +- pinctrl-single,power-source : value of setting power source field + in the pinmux register + +- pinctrl-single,bias-mask : mask of setting bias value in the pinmux + register + +- pinctrl-single,bias-disable : value of disabling bias in the pinmux + register + +- pinctrl-single,bias-pull-down : value of setting bias pull down in + the pinmux register + +- pinctrl-single,bias-pull-up : value of setting bias pull up in the + pinmux register + +- pinctrl-single,bias : value of setting bias in the pinmux register + +- pinctrl-single,input-schmitt-mask : mask of setting input schmitt + in the pinmux register + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -42,6 +77,15 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. +In case pinctrl device supports gpio function, it needs to define gpio range. +All the phandles of gpio range list should be set in below: + + pinctrl-single,gpio-ranges = <[phandle of gpio range]>; + + [phandle of gpio range]: { + pinctrl-single,gpio = <0 55 0x0dc>; + pinctrl-single,gpio-func = <0>; + }; Example: /* SoC common file */ @@ -76,6 +120,28 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux@d401e000 { + compatible = "pinctrl-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + pinctrl-single,gpio-ranges = <&gpiorange0 &gpiorange1>; +}; + +gpiorange0: gpiorange@d401e0dc { + pinctrl-single,gpio = <0 55 0x0dc>; + pinctrl-single,gpio-func = <0>; +}; + +gpiorange1: gpiorange@d401e2f0 { + pinctrl-single,gpio = <55 5 0x2f0>; + pinctrl-single,gpio-func = <1>; +}; + + /* board specific .dts file */ &pmx_core {