From patchwork Thu Nov 1 09:26:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 1683741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 885693FCDF for ; Thu, 1 Nov 2012 09:35:54 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TTr9P-0007Vu-FW; Thu, 01 Nov 2012 09:33:25 +0000 Received: from smtp1.mail.ru ([94.100.176.129]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TTr4j-0005Uq-Gp for linux-arm-kernel@lists.infradead.org; Thu, 01 Nov 2012 09:28:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=EZfM0ZdjZBtTQgIroGUp9sKwr/IUaCO24zgtcpDDci0=; b=XKjlG36ezctr7XS9hVA49oXhyeeeIsD8NUiU11rVdRGoV5VlgXgmAfi8Xye5FItek71Ia0Pbs3krpQOFkSdhUf5YZZju8B70Sllqz6pkCFDzHL2xk8BBLV3bZlX+imlF; Received: from [188.134.40.128] (port=33548 helo=shc.zet) by smtp1.mail.ru with esmtpa (envelope-from ) id 1TTr4i-0001ZR-5K; Thu, 01 Nov 2012 13:28:32 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/15] ARM: clps711x: Add FIQ interrupt handling Date: Thu, 1 Nov 2012 13:26:40 +0400 Message-Id: <1351762006-27368-10-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.7.8.6 In-Reply-To: <1351762006-27368-1-git-send-email-shc_work@mail.ru> References: <1351762006-27368-1-git-send-email-shc_work@mail.ru> X-Spam: Not detected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121101_052834_524420_6CD128E8 X-CRM114-Status: GOOD ( 14.43 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [94.100.176.129 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (shc_work[at]mail.ru) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Olof Johansson , Russell King , Alexander Shiyan , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org CLPS711X-target CPU can have a several FIQ interrupts. With this patch we adds handling for a one which will be used for ALSA PCM later. Since FIQ have a separate handler we only add "mask" and "unmask" calls which will used for enable/disable_irq functions. Signed-off-by: Alexander Shiyan --- arch/arm/mach-clps711x/common.c | 37 ++++++++++++++++++++++- arch/arm/mach-clps711x/common.h | 2 +- arch/arm/mach-clps711x/include/mach/clps711x.h | 3 ++ 3 files changed, 39 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 3cc0380..c5d0c63 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -91,7 +92,7 @@ static void int1_unmask(struct irq_data *d) } static struct irq_chip int1_chip = { - .name = "Interrupt Vector 1 ", + .name = "Interrupt Vector 1", .irq_ack = int1_ack, .irq_eoi = int1_eoi, .irq_mask = int1_mask, @@ -128,13 +129,37 @@ static void int2_unmask(struct irq_data *d) } static struct irq_chip int2_chip = { - .name = "Interrupt Vector 2 ", + .name = "Interrupt Vector 2", .irq_ack = int2_ack, .irq_eoi = int2_eoi, .irq_mask = int2_mask, .irq_unmask = int2_unmask, }; +static void int3_mask(struct irq_data *d) +{ + u32 intmr3; + + intmr3 = clps_readl(INTMR3); + intmr3 &= ~(1 << (d->irq - 32)); + clps_writel(intmr3, INTMR3); +} + +static void int3_unmask(struct irq_data *d) +{ + u32 intmr3; + + intmr3 = clps_readl(INTMR3); + intmr3 |= 1 << (d->irq - 32); + clps_writel(intmr3, INTMR3); +} + +static struct irq_chip int3_chip = { + .name = "Interrupt Vector 3", + .irq_mask = int3_mask, + .irq_unmask = int3_unmask, +}; + struct clps711x_irqdesc { int nr; struct irq_chip *chip; @@ -190,6 +215,14 @@ void __init clps711x_init_irq(void) set_irq_flags(clps711x_irqdescs[i].nr, IRQF_VALID | IRQF_PROBE); } + + if (IS_ENABLED(CONFIG_FIQ)) { + irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip, + handle_bad_irq); + set_irq_flags(IRQ_DAIINT, + IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); + init_FIQ(0); + } } inline u32 fls16(u32 x) diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h index 9d3e9db..d12d647 100644 --- a/arch/arm/mach-clps711x/common.h +++ b/arch/arm/mach-clps711x/common.h @@ -4,7 +4,7 @@ * Common bits. */ -#define CLPS711X_NR_IRQS (30) +#define CLPS711X_NR_IRQS (33) #define CLPS711X_NR_GPIO (4 * 8 + 3) #define CLPS711X_GPIO(port,bit) ((port) * 8 + (bit)) diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 1f4728d..01d1b95 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -298,4 +298,7 @@ #define IRQ_UTXINT2 (16 + 12) #define IRQ_URXINT2 (16 + 13) +/* INTSR3 Interrupts */ +#define IRQ_DAIINT (32 + 0) + #endif /* __MACH_CLPS711X_H */