From patchwork Sat Nov 3 14:45:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 1692451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 728613FCDE for ; Sat, 3 Nov 2012 14:23:06 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TUeb4-000494-W0; Sat, 03 Nov 2012 14:21:16 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TUeao-000442-Og for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 14:21:00 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCX00K4T16XUI20@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 23:20:57 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-41-50952849683f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id D6.1A.12699.94825905; Sat, 03 Nov 2012 23:20:57 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCX00DCN163LTA0@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 23:20:57 +0900 (KST) From: Thomas Abraham To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/5] ARM: Exynos: prepare an array of MCT interrupt numbers and use it Date: Sat, 03 Nov 2012 20:15:35 +0530 Message-id: <1351953938-13487-3-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org> References: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIJMWRmVeSWpSXmKPExsVy+t9jQV1PjakBBv8OCllsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6MKXubmAruqVRsun6DuYFxl1wXIyeHhICJxKNn+5ggbDGJC/fW s3UxcnEICUxnlDj8ZR0rSEJIYD2TxKyuCBCbTcBA4tHCd+wgtoiAhsSUrsfsIA3MAosYJfo2 zwKbJCwQITGz+QIziM0ioCpx5NMyIJuDg1fAU+LzNU6IZUoSG3qPgpVzCnhJvHj+nAVil6fE nofHWCYw8i5gZFjFKJpakFxQnJSea6RXnJhbXJqXrpecn7uJEezxZ9I7GFc1WBxiFOBgVOLh NZCYEiDEmlhWXJl7iFGCg1lJhLdDbGqAEG9KYmVValF+fFFpTmrxIUZpDhYlcd5mj5QAIYH0 xJLU7NTUgtQimCwTB6dUA6PR9LceqSLWGy7+eX2upfTRMW22AtXZ3NbnpYVfHfoW7Xd9iur8 +//XccQebrXWX3pJ4L/H12fvzrwOSTx5YWeMyU9J0wmH1x0UdunmXdKbsM7x7/S3h+JeKJSZ +xn8WBU247XfCrGq8Ik3rRxEMpzf+kzaG6Reb1glfS5Ar/3SPOHY19zmN5iUWIozEg21mIuK EwGuKjiN9AEAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121103_102059_138371_A564D742 X-CRM114-Status: GOOD ( 13.78 ) X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, devicetree-discuss@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org, Changhwan Youn , t.figa@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Instead of using soc_is_xxx macro at more than one place in the MCT controller driver to decide the MCT interrpt number to be setup, populate a table of known MCT global and local timer interrupts and use the values in table to setup the MCT interrupts. This also helps in adding device tree support for MCT controller driver by allowing the driver to retrieve interrupt numbers from device tree and populating them into this table, thereby supporting both legacy and dt functionality to co-exist. Cc: Changhwan Youn Signed-off-by: Thomas Abraham --- arch/arm/mach-exynos/mct.c | 57 +++++++++++++++++++++++++++---------------- 1 files changed, 36 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index c3c4799..d65d0c7 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -64,9 +64,22 @@ enum { MCT_INT_PPI }; +enum { + MCT_G0_IRQ, + MCT_G1_IRQ, + MCT_G2_IRQ, + MCT_G3_IRQ, + MCT_L0_IRQ, + MCT_L1_IRQ, + MCT_L2_IRQ, + MCT_L3_IRQ, + MCT_NR_IRQS, +}; + static void __iomem *reg_base; static unsigned long clk_rate; static unsigned int mct_int_type; +static int mct_irqs[MCT_NR_IRQS]; struct mct_clock_event_device { struct clock_event_device *evt; @@ -285,11 +298,7 @@ static void exynos4_clockevent_init(void) clockevent_delta2ns(0xf, &mct_comp_device); mct_comp_device.cpumask = cpumask_of(0); clockevents_register_device(&mct_comp_device); - - if (soc_is_exynos5250()) - setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); - else - setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq); + setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); } #ifdef CONFIG_LOCAL_TIMERS @@ -413,7 +422,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) { struct mct_clock_event_device *mevt; unsigned int cpu = smp_processor_id(); - int mct_lx_irq; mevt = this_cpu_ptr(&percpu_mct_tick); mevt->evt = evt; @@ -440,21 +448,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) if (mct_int_type == MCT_INT_SPI) { if (cpu == 0) { - mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 : - EXYNOS5_IRQ_MCT_L0; mct_tick0_event_irq.dev_id = mevt; - evt->irq = mct_lx_irq; - setup_irq(mct_lx_irq, &mct_tick0_event_irq); + evt->irq = mct_irqs[MCT_L0_IRQ]; + setup_irq(evt->irq, &mct_tick0_event_irq); } else { - mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 : - EXYNOS5_IRQ_MCT_L1; mct_tick1_event_irq.dev_id = mevt; - evt->irq = mct_lx_irq; - setup_irq(mct_lx_irq, &mct_tick1_event_irq); - irq_set_affinity(mct_lx_irq, cpumask_of(1)); + evt->irq = mct_irqs[MCT_L1_IRQ]; + setup_irq(evt->irq, &mct_tick1_event_irq); + irq_set_affinity(evt->irq, cpumask_of(1)); } } else { - enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); + enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); } return 0; @@ -470,7 +474,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt) else remove_irq(evt->irq, &mct_tick1_event_irq); else - disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER); + disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); } static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { @@ -492,11 +496,11 @@ static void __init exynos4_timer_resources(void) if (mct_int_type == MCT_INT_PPI) { int err; - err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, + err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], exynos4_mct_tick_isr, "MCT", &percpu_mct_tick); WARN(err, "MCT: can't request IRQ %d (%d)\n", - EXYNOS_IRQ_MCT_LOCALTIMER, err); + mct_irqs[MCT_L0_IRQ], err); } local_timer_register(&exynos4_mct_tick_ops); @@ -505,10 +509,21 @@ static void __init exynos4_timer_resources(void) static void __init exynos4_timer_init(void) { - if ((soc_is_exynos4210()) || (soc_is_exynos5250())) + if (soc_is_exynos4210()) { + mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; + mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0; + mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1; mct_int_type = MCT_INT_SPI; - else + } else if (soc_is_exynos5250()) { + mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0; + mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0; + mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1; + mct_int_type = MCT_INT_SPI; + } else { + mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; + mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER; mct_int_type = MCT_INT_PPI; + } exynos4_timer_resources(); exynos4_clocksource_init();