From patchwork Sat Nov 3 14:45:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 1692471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 195B3DFB7B for ; Sat, 3 Nov 2012 14:23:24 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TUebO-0004En-Lg; Sat, 03 Nov 2012 14:21:34 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TUeax-000466-2a for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 14:21:10 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCX007581730O50@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 23:21:03 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-b0-5095284f3e23 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id B4.CD.01231.F4825905; Sat, 03 Nov 2012 23:21:03 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCX00DCN163LTA0@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 23:21:03 +0900 (KST) From: Thomas Abraham To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/5] ARM: Exynos: add device tree support for MCT controller driver Date: Sat, 03 Nov 2012 20:15:36 +0530 Message-id: <1351953938-13487-4-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org> References: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEJMWRmVeSWpSXmKPExsVy+t9jQV1/jakBBvPviFpsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6Mfb8eMxfcNq/Y8YS7gfG0bhcjJ4eEgInEq9kvGCFsMYkL99az dTFycQgJTGeUWNf1EspZzyTx9MA6NpAqNgEDiUcL37GD2CICGhJTuh6zgxQxCyxilOjbPIsJ JCEsECox5fsjsLEsAqoSa88eYgWxeQU8JXZ3rGOHWKcksaH3KFg9p4CXxIvnz1lAbCGgmj0P j7FMYORdwMiwilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyPY58+kdjCubLA4xCjAwajEw3uB b0qAEGtiWXFl7iFGCQ5mJRHeDrGpAUK8KYmVValF+fFFpTmpxYcYpTlYlMR5mz1SAoQE0hNL UrNTUwtSi2CyTBycUg2M6+I4HrlFTb9X4hnyf/X76a5OJRONI1R1L8UVrDRNyJn5VXiHRY5p 6iOBv0cPF2ma3Xr/tFZ52YZwLqkpj2P//o4w/GwqZnv3xxSV/JUXuT0t1Z8Ute7rWPSqadND 1izBwozQvHrVL/sO/C1jExP533vTP2hvXfd50aXOloJHhI/t4ihfpsmsxFKckWioxVxUnAgA p1B78vUBAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121103_102107_680472_477C6B74 X-CRM114-Status: GOOD ( 17.91 ) X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.25 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, devicetree-discuss@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org, Changhwan Youn , t.figa@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Allow the MCT controller base address and interrupts to be obtained from device tree and remove unused static definitions of these. The non-dt support for Exynos5250 is removed but retained for Exynos4210 based platforms. Cc: Changhwan Youn Signed-off-by: Thomas Abraham --- .../bindings/timer/samsung,exynos4210-mct.txt | 70 ++++++++++++++++++++ arch/arm/mach-exynos/include/mach/irqs.h | 6 -- arch/arm/mach-exynos/mct.c | 42 ++++++++---- 3 files changed, 99 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt new file mode 100644 index 0000000..c53fd93 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt @@ -0,0 +1,70 @@ +Samsung's Multi Core Timer (MCT) + +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the +global timer and CPU local timers. The global timer is a 64-bit free running +up-counter and can generate 4 interrupts when the counter reaches one of the +four preset counter values. The CPU local timers are 32-bit free running +down-counters and generates an interrupt when the counter expires. There is +one CPU local timer instantiated in MCT for every CPU in the system. + +Required properties: + +- compatible: should be "samsung,exynos4210-mct". +- reg: base address of the mct controller and length of the address space + it occupies. +- interrupts: the list of interrupts generated by the controller. The following + should be the order of the interrupts specified. The local timer interrupts + should be specified after the four global timer interrupts have been + specified. + + 0: Global Timer Interrupt 0 + 1: Global Timer Interrupt 1 + 2: Global Timer Interrupt 2 + 3: Global Timer Interrupt 3 + 4: Local Timer Interrupt 0 + 5: Local Timer Interrupt 1 + 6: .. + 7: .. + i: Local Timer Interrupt n + +- samsung,mct-nr-local-irqs: The number of local timer interrupts supported + by the MCT controller. + +Example 1: In this example, the system uses only the first global timer + interrupt generated by MCT and the remaining three global timer + interrupts are unused. Two local timer interrupts have been + specified. + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>, + <0 42 0>, <0 48 0>; + samsung,mct-nr-local-irqs = <4>; + }; + +Example 2: In this example, the MCT global and local timer interrupts are + connected to two seperate interrupt controllers. Hence, an + interrupt-map is created to map the interrupts to the respective + interrupt controllers. + + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + samsung,mct-nr-local-irqs = <2>; + + mct_map: mct-map { + compatible = "samsung,mct-map"; + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &combiner 23 3>, + <0x4 0 &gic 0 120 0>, + <0x5 0 &gic 0 121 0>; + }; + }; diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 6da3115..03c9f04 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -30,8 +30,6 @@ /* For EXYNOS4 and EXYNOS5 */ -#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) - #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) /* For EXYNOS4 SoCs */ @@ -320,8 +318,6 @@ #define EXYNOS5_IRQ_CEC IRQ_SPI(114) #define EXYNOS5_IRQ_SATA IRQ_SPI(115) -#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) -#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) @@ -411,8 +407,6 @@ #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) -#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) -#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index d65d0c7..f7792b8 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include #include #include @@ -483,14 +486,16 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { }; #endif /* CONFIG_LOCAL_TIMERS */ -static void __init exynos4_timer_resources(void) +static void __init exynos4_timer_resources(struct device_node *np) { struct clk *mct_clk; mct_clk = clk_get(NULL, "xtal"); clk_rate = clk_get_rate(mct_clk); - reg_base = S5P_VA_SYSTIMER; + reg_base = (np) ? of_iomap(np, 0) : S5P_VA_SYSTIMER; + if (!reg_base) + panic("%s: unable to ioremap mct address space\n", __func__); #ifdef CONFIG_LOCAL_TIMERS if (mct_int_type == MCT_INT_PPI) { @@ -509,23 +514,34 @@ static void __init exynos4_timer_resources(void) static void __init exynos4_timer_init(void) { - if (soc_is_exynos4210()) { + struct device_node *np; + u32 nr_irqs, i; + + np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct"); + if (np) { + if (of_machine_is_compatible("samsung,exynos4210") || + of_machine_is_compatible("samsung,exynos5250")) + mct_int_type = MCT_INT_SPI; + else + mct_int_type = MCT_INT_PPI; + + if (of_property_read_u32(np, "samsung,mct-nr-local-irqs", + &nr_irqs)) + panic("%s: number of local irqs not specified\n", + __func__); + + mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); + for (i = 0; i < nr_irqs; i++) + mct_irqs[MCT_L0_IRQ + i] = + irq_of_parse_and_map(np, MCT_L0_IRQ + i); + } else if (soc_is_exynos4210()) { mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0; mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1; mct_int_type = MCT_INT_SPI; - } else if (soc_is_exynos5250()) { - mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0; - mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0; - mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1; - mct_int_type = MCT_INT_SPI; - } else { - mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; - mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER; - mct_int_type = MCT_INT_PPI; } - exynos4_timer_resources(); + exynos4_timer_resources(np); exynos4_clocksource_init(); exynos4_clockevent_init(); }