From patchwork Mon Nov 5 09:12:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 1695571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id F1B113FCA5 for ; Mon, 5 Nov 2012 09:31:50 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVIzr-0006RZ-4g; Mon, 05 Nov 2012 09:29:31 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TVIzn-0006Q4-Nc for linux-arm-kernel@lists.infradead.org; Mon, 05 Nov 2012 09:29:28 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA59TKCV012307; Mon, 5 Nov 2012 03:29:21 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA59TKt2007996; Mon, 5 Nov 2012 14:59:20 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Mon, 5 Nov 2012 14:59:19 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id qA59TJGl021683; Mon, 5 Nov 2012 14:59:19 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id 20AE7158002; Mon, 5 Nov 2012 14:59:19 +0530 (IST) Received: from localhost.localdomain (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id qA59TI723254; Mon, 5 Nov 2012 14:59:18 +0530 (IST) From: "Philip, Avinash" To: , , , , Subject: [PATCH 2/8] ARM: am33xx: clk: Add optional clock for EHRPWM Date: Mon, 5 Nov 2012 14:42:23 +0530 Message-ID: <1352106749-9437-3-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1352106749-9437-1-git-send-email-avinashphilip@ti.com> References: <1352106749-9437-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121105_042927_957781_AB7E16D2 X-CRM114-Status: GOOD ( 13.31 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.41 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-doc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, hvaibhav@ti.com, gururaja.hebbar@ti.com, anilkumar@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org EHRPWM module requires explicit clock gating from control module. Hence add clock node in clock tree for EHRPWM modules. Signed-off-by: Philip, Avinash --- :100644 100644 17e3de5... 833260f... M arch/arm/mach-omap2/clock33xx_data.c :100644 100644 a89e825... c0e34e6... M arch/arm/mach-omap2/control.h arch/arm/mach-omap2/clock33xx_data.c | 37 ++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/control.h | 8 +++++++ 2 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index 17e3de5..833260f 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -995,6 +995,40 @@ static struct clk wdt1_fck = { }; /* + * PWMSS Time based module clock node. This node is + * requred to enable clock gating for EHRPWM TBCLK. + */ +static struct clk ehrpwm0_tbclk = { + .name = "ehrpwm0_tbclk", + .clkdm_name = "l4ls_clkdm", + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + .enable_bit = AM33XX_PWMSS0_TBCLKEN_SHIFT, + .ops = &clkops_omap2_dflt, + .parent = &l4ls_gclk, + .recalc = &followparent_recalc, +}; + +static struct clk ehrpwm1_tbclk = { + .name = "ehrpwm1_tbclk", + .clkdm_name = "l4ls_clkdm", + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + .enable_bit = AM33XX_PWMSS1_TBCLKEN_SHIFT, + .ops = &clkops_omap2_dflt, + .parent = &l4ls_gclk, + .recalc = &followparent_recalc, +}; + +static struct clk ehrpwm2_tbclk = { + .name = "ehrpwm2_tbclk", + .clkdm_name = "l4ls_clkdm", + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + .enable_bit = AM33XX_PWMSS2_TBCLKEN_SHIFT, + .ops = &clkops_omap2_dflt, + .parent = &l4ls_gclk, + .recalc = &followparent_recalc, +}; + +/* * clkdev */ static struct omap_clk am33xx_clks[] = { @@ -1074,6 +1108,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "ehrpwm0_tbclk", &ehrpwm0_tbclk, CK_AM33XX), + CLK(NULL, "ehrpwm1_tbclk", &ehrpwm1_tbclk, CK_AM33XX), + CLK(NULL, "ehrpwm2_tbclk", &ehrpwm2_tbclk, CK_AM33XX), }; int __init am33xx_clk_init(void) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a89e825..c0e34e6 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -357,6 +357,14 @@ #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) +/* AM33XX PWMSS Control register */ +#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664 + +/* AM33XX PWMSS Control bitfields */ +#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0 +#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1 +#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2 + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c