From patchwork Mon Nov 5 09:12:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 1695651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 1624BDF2AB for ; Mon, 5 Nov 2012 09:34:00 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVJ0y-0006zn-HZ; Mon, 05 Nov 2012 09:30:42 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TVJ0G-0006cc-OD for linux-arm-kernel@lists.infradead.org; Mon, 05 Nov 2012 09:29:58 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA59TmUj017173; Mon, 5 Nov 2012 03:29:48 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA59TlCv008121; Mon, 5 Nov 2012 14:59:47 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Mon, 5 Nov 2012 14:59:47 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id qA59Tlxm021709; Mon, 5 Nov 2012 14:59:47 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id 148B8158002; Mon, 5 Nov 2012 14:59:47 +0530 (IST) Received: from localhost.localdomain (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id qA59Tj723263; Mon, 5 Nov 2012 14:59:45 +0530 (IST) From: "Philip, Avinash" To: , , , , Subject: [PATCH 5/8] pwm: pwm-tiehrpwm: Add device-tree binding support for EHRPWM driver Date: Mon, 5 Nov 2012 14:42:26 +0530 Message-ID: <1352106749-9437-6-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1352106749-9437-1-git-send-email-avinashphilip@ti.com> References: <1352106749-9437-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121105_042957_169177_58A24D38 X-CRM114-Status: GOOD ( 20.05 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.40 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Rob Landley , linux-doc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, hvaibhav@ti.com, gururaja.hebbar@ti.com, Grant Likely , Rob Herring , anilkumar@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add support for device-tree binding for EHRWPM driver. Also size of #pwm-cells set to 3 to support PWM channel number, PWM period & polarity configuration from device tree. Also enable clock gating in PWM subsystem common config space. Also when here set .owner member in platform_driver structure to THIS_MODULE. Signed-off-by: Philip, Avinash Cc: Grant Likely Cc: Rob Herring Cc: Rob Landley --- Second version - Combined with HWMOD changes & DT bindings. - Remove the custom of_xlate support. :000000 100644 0000000... aa2ed0a... A Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt :100644 100644 d3c1dff... 1e63652... M drivers/pwm/pwm-tiehrpwm.c .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 25 +++++++++++++ drivers/pwm/pwm-tiehrpwm.c | 37 ++++++++++++++++++- 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt new file mode 100644 index 0000000..aa2ed0a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -0,0 +1,25 @@ +TI SOC EHRPWM based PWM controller + +Required properties: +- compatible : Must be "ti,am33xx-ehrpwm" +- #pwm-cells: Should be 3. Number of cells being used to specify PWM property. + First cell specifies the per-chip index of the PWM to use, the second + cell is the period cycle in nanoseconds and bit 0 in the third cell is + used to encode the polarity of PWM output. +- reg: physical base address and size of the registers map. + +Optional properties: +- ti,hwmods: Name of the hwmod associated to the EHRPWM: + "ehrpwm", being the 0-based instance number from the HW spec +- tbclkgating: platforms require tbclk gating from control module + should populate + +Example: + +ehrpwm0: ehrpwm@0 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x100>; + ti,hwmods = "ehrpwm0"; + tbclkgating; +}; diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index d3c1dff..1e63652 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -25,6 +25,10 @@ #include #include #include +#include +#include + +#include "tipwmss.h" /* EHRPWM registers and bits definitions */ @@ -107,6 +111,10 @@ #define AQCSFRC_CSFA_FRCHIGH BIT(1) #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) +#define EPWMCLK_EN_SHIFT 8 + +#define PWM_CELL_SIZE 3 + #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ struct ehrpwm_pwm_chip { @@ -392,12 +400,27 @@ static const struct pwm_ops ehrpwm_pwm_ops = { .owner = THIS_MODULE, }; +#ifdef CONFIG_OF +static const struct of_device_id ehrpwm_of_match[] = { + { + .compatible = "ti,am33xx-ehrpwm", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ehrpwm_of_match); +#endif + static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) { int ret; struct resource *r; struct clk *clk; struct ehrpwm_pwm_chip *pc; + struct pinctrl *pinctrl; + + pinctrl = devm_pinctrl_get_select_default(&pdev->dev); + if (IS_ERR(pinctrl)) + dev_warn(&pdev->dev, "failed to configure pins from driver\n"); pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); if (!pc) { @@ -419,6 +442,7 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) pc->chip.dev = &pdev->dev; pc->chip.ops = &ehrpwm_pwm_ops; + pc->chip.of_pwm_n_cells = PWM_CELL_SIZE; pc->chip.base = -1; pc->chip.npwm = NUM_PWM_CHANNEL; @@ -437,8 +461,11 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); return ret; } - pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_EN_SHIFT, true); + pm_runtime_put_sync(&pdev->dev); + platform_set_drvdata(pdev, pc); return 0; } @@ -447,6 +474,10 @@ static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) { struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); + pm_runtime_get_sync(&pdev->dev); + pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_EN_SHIFT, false); + pm_runtime_put_sync(&pdev->dev); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); return pwmchip_remove(&pc->chip); @@ -454,7 +485,9 @@ static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) static struct platform_driver ehrpwm_pwm_driver = { .driver = { - .name = "ehrpwm", + .name = "ehrpwm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ehrpwm_of_match), }, .probe = ehrpwm_pwm_probe, .remove = __devexit_p(ehrpwm_pwm_remove),