| Message ID | 1352106749-9437-7-git-send-email-avinashphilip@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Nov 05, 2012 at 14:42:27, Philip, Avinash wrote: [...] > + /* Some platforms require explicit tbclk gating */ > + if (of_property_read_bool(pdev->dev.of_node, "tbclkgating")) { > + pc->tbclk = clk_get(&pdev->dev, "tbclk"); > + if (IS_ERR(pc->tbclk)) { > + dev_err(&pdev->dev, "Could not get EHRPWM TBCLK\n"); > + return PTR_ERR(pc->tbclk); > + } > + } > + > + /* Enable tbclk & leave */ > + if (pc->tbclk) > + clk_enable(pc->tbclk); > + Here also why are you leaving this clock always running? Regards, Vaibhav
On Tue, Nov 06, 2012 at 12:16:13, Bedia, Vaibhav wrote: > On Mon, Nov 05, 2012 at 14:42:27, Philip, Avinash wrote: > [...] > > > + /* Some platforms require explicit tbclk gating */ > > + if (of_property_read_bool(pdev->dev.of_node, "tbclkgating")) { > > + pc->tbclk = clk_get(&pdev->dev, "tbclk"); > > + if (IS_ERR(pc->tbclk)) { > > + dev_err(&pdev->dev, "Could not get EHRPWM TBCLK\n"); > > + return PTR_ERR(pc->tbclk); > > + } > > + } > > + > > + /* Enable tbclk & leave */ > > + if (pc->tbclk) > > + clk_enable(pc->tbclk); > > + > > Here also why are you leaving this clock always running? This is an additional clock gating for EHRPWM functional clock from control module. The enabling of this clock to pwm_enable & disabling to pwm_disable. I will correct it. Thanks Avinash > > Regards, > Vaibhav >
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 1e63652..cf69da3 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -123,6 +123,7 @@ struct ehrpwm_pwm_chip { void __iomem *mmio_base; unsigned long period_cycles[NUM_PWM_CHANNEL]; enum pwm_polarity polarity[NUM_PWM_CHANNEL]; + struct clk *tbclk; }; static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) @@ -461,6 +462,20 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); return ret; } + + /* Some platforms require explicit tbclk gating */ + if (of_property_read_bool(pdev->dev.of_node, "tbclkgating")) { + pc->tbclk = clk_get(&pdev->dev, "tbclk"); + if (IS_ERR(pc->tbclk)) { + dev_err(&pdev->dev, "Could not get EHRPWM TBCLK\n"); + return PTR_ERR(pc->tbclk); + } + } + + /* Enable tbclk & leave */ + if (pc->tbclk) + clk_enable(pc->tbclk); + pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_EN_SHIFT, true); @@ -478,6 +493,8 @@ static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_EN_SHIFT, false); pm_runtime_put_sync(&pdev->dev); + if (pc->tbclk) + clk_disable(pc->tbclk); pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); return pwmchip_remove(&pc->chip);
Some platforms (like AM33XX) requires clock gating from control module explicitly. So adding optional TBCLK handling if DT node populated with tbclkgating. This helps the driver can coexist for Davinci platforms. Signed-off-by: Philip, Avinash <avinashphilip@ti.com> --- :100644 100644 1e63652... cf69da3... M drivers/pwm/pwm-tiehrpwm.c drivers/pwm/pwm-tiehrpwm.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-)