From patchwork Tue Nov 6 04:38:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmavathi Venna X-Patchwork-Id: 1702641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 99C843FCF7 for ; Tue, 6 Nov 2012 04:38:44 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVatm-0008BF-MD; Tue, 06 Nov 2012 04:36:27 +0000 Received: from mailout4.samsung.com ([203.254.224.34]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVati-00089n-1m for linux-arm-kernel@lists.infradead.org; Tue, 06 Nov 2012 04:36:23 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD10025SU4KUZ00@mailout4.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 06 Nov 2012 13:36:20 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 7A.65.12699.4C398905; Tue, 06 Nov 2012 13:36:20 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-3c-509893c40e6a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id A9.65.12699.4C398905; Tue, 06 Nov 2012 13:36:20 +0900 (KST) Received: from padma-linuxpc.sisodomain.com ([107.108.83.35]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD100EPMU2TFSA0@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 06 Nov 2012 13:36:20 +0900 (KST) From: Padmavathi Venna To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH V3] ARM: EXYNOS5: Add clocks for EXYNOS5 Audio Subsystem. Date: Tue, 06 Nov 2012 10:08:51 +0530 Message-id: <1352176731-16199-1-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 1.7.4.4 DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrILMWRmVeSWpSXmKPExsWyRsSkSvfI5BkBBlcXGFlsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6M8+vWsxbMca1Y83MRSwPjf4suRk4OCQETiZ+bf7NC2GISF+6t Z+ti5OIQEljKKHFv4zp2mKIZK5YzQSSmM0p8fj+NGcLZyiRxZ2IrUAsHB5uAjkTLWRcQU0TA W2L5NUUQk1kgR6KxTQVkjLCAp8StC4fBdrEIqEqs2fSeDcTmFXCWmHntGTPEKgWJY1O/QtUI SHybfIgFZIyEgKzEpgNgSyUEdrBJfGs4xwhRLylxcMUNlgmMggsYGVYxiqYWJBcUJ6XnGukV J+YWl+al6yXn525iBIbT6X/PpHcwrmqwOMQowMGoxMMrKDYjQIg1say4MvcQowQHs5IIL8ed 6QFCvCmJlVWpRfnxRaU5qcWHGH2ALpnILCWanA8M9bySeENjE3NTY1NLIyMzU1McwkrivM0e KQFCAumJJanZqakFqUUw45g4OKUaGPk5vxRyWr6cNCeZ79WT/GX7LunwzeptONDD2R2dY6/p /8lvQaFVd0x3Zs2HxW1JzDEqOn1xsf+/By3c8CTo+LdlzcxfdtfPv7p2/dacT56Ls3dZMx7j 1V7477mTfmdkSPp6N8nHUasOMgtO0IkKnfhimsrt7fdWL81fZOR9uUur9uNfuUnlr5RYijMS DbWYi4oTAbAqAN1UAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrALMWRmVeSWpSXmKPExsVy+t9jQd0jk2cEGLx6IW+x6fE1VgdGj81L 6gMYoxoYbTJSE1NSixRS85LzUzLz0m2VvIPjneNNzQwMdQ0tLcyVFPISc1NtlVx8AnTdMnOA pioplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM86vW89aMMe1Ys3PRSwN jP8tuhg5OSQETCRmrFjOBGGLSVy4t56ti5GLQ0hgOqPE5/fTmCGcrUwSdya2AmU4ONgEdCRa zrqAmCIC3hLLrymCmMwCORKNbSogY4QFPCVuXTjMCmKzCKhKrNn0ng3E5hVwlph57RkzxCoF iWNTv7JOYORewMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93EyM4WJ9J72Bc1WBxiFGAg1GJ h1dQbEaAEGtiWXFl7iFGCQ5mJRFejjvTA4R4UxIrq1KL8uOLSnNSiw8x+gBtn8gsJZqcD4yk vJJ4Q2MTc1NjU0sTCxMzSxzCSuK8zR4pAUIC6YklqdmpqQWpRTDjmDg4pRoYxdOyAla+2yMg vb7XS0yc+8mBWdxfPtVcn/7g7Y/EOyFPrFaszpgWGx/+xtPRUU2xpNDFwPCww5uJfle8b1c3 3fzjeJ/VcrdFxC3J3LRdVoVKE9L2XTu57bD3/k0FQbKPnj5Lk+b4YPv7WO/Vp6l/vqeUsPmJ H/y6ju3Bku4Hrz4995i9/HWmshJLcUaioRZzUXEiALH2K6KDAgAA X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121105_233622_686968_3B99CB32 X-CRM114-Status: GOOD ( 20.45 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.34 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: sbkim73@samsung.com, kgene.kim@samsung.com, olofj@google.com, ben-linux@fluff.org, padma.v@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds all the required clock instances for audio subsystem and adds the clock alias names for sclk-i2s and i2s-bus clks. This patch also do the static mapping of audss clock base address to control audss clocks in CMU clock framework. Signed-off-by: Padmavathi Venna Acked-by: Sangbeom Kim --- Changes since V2: - Rebased on 3.7-rc3 Changes since V1: - Rebased on 3.6-rc6 - Modified some of the clk names as suggested by Kukjin Kim - Added NULL in place of cdclk of sclk_audio0 src list as it is machine dependent and I am not using it as src. arch/arm/mach-exynos/clock-exynos5.c | 117 ++++++++++++++++++++++++ arch/arm/mach-exynos/common.c | 5 + arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/include/mach/regs-audss.h | 7 +- arch/arm/plat-samsung/include/plat/map-s5p.h | 2 + 5 files changed, 131 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index a88e0d9..7a61d41 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -24,6 +24,7 @@ #include #include +#include #include #include "common.h" @@ -166,6 +167,16 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable); } +static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable); +} + +static int exynos5_clk_audss_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS_CLKGATE_AUDSS, clk, enable); +} + static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable); @@ -707,6 +718,11 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 3), }, { .name = "iis", + .devname = "samsung-i2s.0", + .enable = exynos5_clk_audss_ctrl, + .ctrlbit = (3 << 2), + }, { + .name = "iis", .devname = "samsung-i2s.1", .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 20), @@ -717,6 +733,11 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 21), }, { .name = "pcm", + .devname = "samsung-pcm.0", + .enable = exynos5_clk_audss_ctrl, + .ctrlbit = (3 << 4), + }, { + .name = "pcm", .devname = "samsung-pcm.1", .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 22), @@ -958,6 +979,95 @@ static struct clk exynos5_init_clocks_on[] = { } }; +static struct clk *clkset_sclk_audio0_list[] = { + [0] = NULL, + [1] = &clk_ext_xtal_mux, + [2] = &exynos5_clk_sclk_hdmi27m, + [3] = &exynos5_clk_sclk_dptxphy, + [4] = &exynos5_clk_sclk_usbphy, + [5] = &exynos5_clk_sclk_hdmiphy, + [6] = &exynos5_clk_mout_mpll.clk, + [7] = &exynos5_clk_mout_epll.clk, + [8] = &exynos5_clk_sclk_vpll.clk, + [9] = &exynos5_clk_mout_cpll.clk, +}; + +static struct clksrc_sources exynos5_clkset_sclk_audio0 = { + .sources = clkset_sclk_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), +}; + +static struct clksrc_clk exynos5_clk_sclk_audio0 = { + .clk = { + .name = "sclk-audio0", + .enable = exynos5_clksrc_mask_maudio_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos5_clkset_sclk_audio0, + .reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 }, +}; + +static struct clk *exynos5_clkset_mout_audss_list[] = { + &clk_ext_xtal_mux, + &clk_fout_epll, +}; + +static struct clksrc_sources clkset_mout_audss = { + .sources = exynos5_clkset_mout_audss_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_audss_list), +}; + +static struct clksrc_clk exynos5_clk_mout_audss = { + .clk = { + .name = "mout_audss", + }, + .sources = &clkset_mout_audss, + .reg_src = { .reg = EXYNOS_CLKSRC_AUDSS, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos5_clkset_sclk_i2s_list[] = { + [0] = &exynos5_clk_mout_audss.clk, + [1] = NULL, + [2] = &exynos5_clk_sclk_audio0.clk, +}; + +static struct clksrc_sources exynos5_clkset_sclk_i2s = { + .sources = exynos5_clkset_sclk_i2s_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_i2s_list), +}; + +static struct clksrc_clk exynos5_clk_sclk_i2s = { + .clk = { + .name = "sclk-i2s", + .devname = "samsung-i2s.0", + .enable = exynos5_clk_audss_ctrl, + .ctrlbit = (1 << 3), + }, + .sources = &exynos5_clkset_sclk_i2s, + .reg_src = { .reg = EXYNOS_CLKSRC_AUDSS, .shift = 2, .size = 2 }, + .reg_div = { .reg = EXYNOS_CLKDIV_AUDSS, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_dout_srp = { + .clk = { + .name = "dout_srp", + .parent = &exynos5_clk_mout_audss.clk, + }, + .reg_div = { .reg = EXYNOS_CLKDIV_AUDSS, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_i2s_bus = { + .clk = { + .name = "i2s-bus", + .devname = "samsung-i2s.0", + .parent = &exynos5_clk_dout_srp.clk, + .enable = exynos5_clk_audss_ctrl, + .ctrlbit = (1 << 2), + }, + .reg_div = { .reg = EXYNOS_CLKDIV_AUDSS, .shift = 4, .size = 4 }, +}; + static struct clk exynos5_clk_pdma0 = { .name = "dma", .devname = "dma-pl330.0", @@ -1334,6 +1444,9 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_mdout_spi1, &exynos5_clk_mdout_spi2, &exynos5_clk_sclk_fimd1, + &exynos5_clk_mout_audss, + &exynos5_clk_dout_srp, + &exynos5_clk_sclk_audio0, }; static struct clk *exynos5_clk_cdev[] = { @@ -1352,6 +1465,8 @@ static struct clksrc_clk *exynos5_clksrc_cdev[] = { &exynos5_clk_sclk_mmc1, &exynos5_clk_sclk_mmc2, &exynos5_clk_sclk_mmc3, + &exynos5_clk_i2s_bus, + &exynos5_clk_sclk_i2s, }; static struct clk_lookup exynos5_clk_lookup[] = { @@ -1370,6 +1485,8 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1), + CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &exynos5_clk_sclk_i2s.clk), + CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &exynos5_clk_i2s_bus.clk), }; static unsigned long exynos5_epll_get_rate(struct clk *clk) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 4e577f6..b4f968a 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -109,6 +109,11 @@ static struct map_desc exynos_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_AUDSS, + .pfn = __phys_to_pfn(EXYNOS_PA_AUDSS), + .length = SZ_4K, + .type = MT_DEVICE, }, }; diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 4192d23..ce15ef5 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -45,6 +45,7 @@ #define EXYNOS5_PA_I2S0 0x03830000 #define EXYNOS5_PA_I2S1 0x12D60000 #define EXYNOS5_PA_I2S2 0x12D70000 +#define EXYNOS_PA_AUDSS 0x03810000 #define EXYNOS4_PA_PCM0 0x03840000 #define EXYNOS4_PA_PCM1 0x13980000 diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h index ca5a8b6..3b23b0d 100644 --- a/arch/arm/mach-exynos/include/mach/regs-audss.h +++ b/arch/arm/mach-exynos/include/mach/regs-audss.h @@ -3,7 +3,7 @@ * Copyright (c) 2011 Samsung Electronics * http://www.samsung.com * - * Exynos4 Audio SubSystem clock register definitions + * Exynos Audio SubSystem clock register definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,4 +15,9 @@ #define EXYNOS4_AUDSS_INT_MEM (0x03000000) +#define EXYNOS_AUDSSREG(x) (S5P_VA_AUDSS + (x)) + +#define EXYNOS_CLKSRC_AUDSS EXYNOS_AUDSSREG(0x0) +#define EXYNOS_CLKDIV_AUDSS EXYNOS_AUDSSREG(0x4) +#define EXYNOS_CLKGATE_AUDSS EXYNOS_AUDSSREG(0x8) #endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index c2d7bda..038aa96 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -40,6 +40,8 @@ #define S5P_VA_GIC_CPU S3C_ADDR(0x02810000) #define S5P_VA_GIC_DIST S3C_ADDR(0x02820000) +#define S5P_VA_AUDSS S3C_ADDR(0x02830000) + #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) #define VA_VIC1 VA_VIC(1)