From patchwork Tue Nov 6 13:15:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1704411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 8FCC4DF230 for ; Tue, 6 Nov 2012 13:19:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVj1N-0001Ca-2T; Tue, 06 Nov 2012 13:16:49 +0000 Received: from eu1sys200aog118.obsmtp.com ([207.126.144.145]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1TVj0a-0000in-4l for linux-arm-kernel@lists.infradead.org; Tue, 06 Nov 2012 13:16:01 +0000 Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKUJkNjDKiy9ptwK8pc3OFGyQKCOxWintg@postini.com; Tue, 06 Nov 2012 13:15:59 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id D920844; Tue, 6 Nov 2012 13:15:20 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id A78844A; Tue, 6 Nov 2012 08:33:46 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 222BDA807B; Tue, 6 Nov 2012 14:15:49 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 6 Nov 2012 14:15:53 +0100 From: Linus Walleij To: Subject: [PATCH 7/9] ARM: ux500: 8500: add pinctrl support for uart1 and uart2 Date: Tue, 6 Nov 2012 14:15:52 +0100 Message-ID: <1352207752-8026-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121106_081600_561334_DF0A0DCB X-CRM114-Status: GOOD ( 15.75 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.145 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Anmar Oueja , Patrice Chotard , Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Patrice Chotard This adds pin mappings for UART1 and UART2. Signed-off-by: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-pins.c | 34 +++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0009ca2..05102ad 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -71,6 +71,10 @@ BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_ENABLED); BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_DISABLED); +BIAS(out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE| + PIN_SLPM_PDIS_DISABLED); +BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| + PIN_SLPM_PDIS_DISABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -128,7 +132,7 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * UART0, we do not mux in u0 here. * uart-0 pins gpio configuration should be kept intact to prevent * a glitch in tx line when the tty dev is opened. Later these pins - * are configured to uart mop500_pins_uart0 + * are configured by uart driver */ DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */ DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */ @@ -139,12 +143,18 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * TODO: is this used on U8500 variants and Snowball really? * The setting on GPIO31 conflicts with magnetometer use on hrefv60 */ - DB8500_MUX_HOG("u2rxtx_c_1", "u2"), - DB8500_MUX_HOG("u2ctsrts_c_1", "u2"), - DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */ - DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */ + /* default state for UART2 */ + DB8500_MUX("u2ctsrts_c_1", "u2", "uart2"), + DB8500_PIN("GPIO31_V3", in_pu, "uart2"), /* CTS */ + DB8500_PIN("GPIO32_V2", out_hi, "uart2"), /* RTS */ + DB8500_MUX("u2rxtx_c_1", "u2", "uart2"), + DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */ + DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */ + /* Sleep state for UART2 */ + DB8500_PIN_SLEEP("GPIO31_V3", in_wkup_pdis, "uart2"), + DB8500_PIN_SLEEP("GPIO32_V2", out_hi_wkup_pdis, "uart2"), + DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"), + DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"), /* * The following pin sets were known as "runtime pins" before being * converted to the pinctrl model. Here we model them as "default" @@ -161,6 +171,13 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"), + /* Mux in UART1 after initialization */ + DB8500_MUX("u1rxtx_a_1", "u1", "uart1"), + DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */ + DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */ + /* Sleep state for UART1 */ + DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"), + DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"), /* MSP1 for ALSA codec */ DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"), DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"), @@ -374,11 +391,8 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), /* Mux in UART1 and set the pull-ups */ DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_MUX_HOG("u1ctsrts_a_1", "u1"), DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */ DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */ - DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */ /* * Runtime stuff: make it possible to mux in the SKE keypad * and bias the pins