From patchwork Thu Nov 22 08:00:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 1783001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id B85F0DF24C for ; Thu, 22 Nov 2012 08:04:18 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TbRid-0002Vz-MJ; Thu, 22 Nov 2012 08:01:07 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TbRi4-0002IY-RQ for linux-arm-kernel@lists.infradead.org; Thu, 22 Nov 2012 08:00:35 +0000 Received: by mail-pa0-f49.google.com with SMTP id bi1so2594481pad.36 for ; Thu, 22 Nov 2012 00:00:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=EuGKW54Du66zK7btlvK5ZB+VHnMG4t3fdR2ARzOW8/c=; b=fuh/W5mGcoQej3x5ZJS7wQrrn3XUBkjp5+mWvUG0rt9soRmS/Rhi3WhEZdQZe3nelE hFhdJMxnR1roUFpzf5qa4QOkz8n9mdc9CmwVJNKJsaG6glLmmt+LQ5AZWHLsjlvzES+g 1rWoHhHnPzWWs0BnOGft1KXVHSIqblS76WaFFY/z3k7BRP3mMQcA20lnY9d4+N1Wtycj elp2IIxB2WLjF3Nzz3LIrxHsiHAIKKEazdYcjWV/r3POVe6Qg7OPaFZumalYZA1VNHM2 L0TpyP2HXLO68uzyOx11ur05/dFKADxml0XjFQlDCxovP7gGVJWcE3RT53XAO2ycdaSV FgoQ== Received: by 10.68.137.167 with SMTP id qj7mr2289178pbb.148.1353571232536; Thu, 22 Nov 2012 00:00:32 -0800 (PST) Received: from xps-iwamatsu.renesas.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPS id s1sm1507624paz.0.2012.11.22.00.00.30 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 00:00:31 -0800 (PST) From: Nobuhiro Iwamatsu To: linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 03/15] ARM: mach-shmobile: Add support OF of INTC for r8a7740 Date: Thu, 22 Nov 2012 17:00:00 +0900 Message-Id: <1353571213-26006-4-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1353571213-26006-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> References: <1353571213-26006-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Gm-Message-State: ALoCoQn/B7Jk2pfJsUWJ8Wnkho+ZRcs/nvGD0dqCJ8XNSyc2fX8AM/UHzcPClNmPXPhf/E1ryUxN X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121122_030033_123626_A4F9469C X-CRM114-Status: GOOD ( 21.65 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nobuhiro Iwamatsu , horms@verge.net.au, magnus.damm@gmail.com, Magnus Damm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This CPU has three interrupt controllers (INTCA, INTCS and INTCA IRQ pins). This supports these. Cc: Magnus Damm Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Simon Horman --- v3 [Nobuhiro Iwamatsu] * Rework the r8a7740 DT INTC init code to reduce the number of #ifdefs. v2 [Simon Horman] * Use #ifdef instead of #if defined * Use CONFIG_OF in place of CONFIG_OF_SH_INTC * Allow OF and non OF code to be compiled in the same binary and provide r8a7740_init_irq_of() as a way to initialise INTC using DT while r8a7740_init_irq() still initialises INTC using the previous code paths. This is because we would like to be able to use a single configuration to compile a kernel for multiple boards and not all r8a7740 boards have DT support yet. v1 [Nobuhiro Iwamatsu] Update r8a7740 Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/intc-r8a7740.c | 69 +++++++++++++++++++++++--- 2 files changed, 64 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index d47e215..8402b5d 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -59,6 +59,7 @@ extern struct clk sh73a0_extal2_clk; extern struct clk sh73a0_extcki_clk; extern struct clk sh73a0_extalr_clk; +extern void r8a7740_init_irq_of(void); extern void r8a7740_init_irq(void); extern void r8a7740_map_io(void); extern void r8a7740_add_early_devices(void); diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c index 9a69a31..a28e0ea 100644 --- a/arch/arm/mach-shmobile/intc-r8a7740.c +++ b/arch/arm/mach-shmobile/intc-r8a7740.c @@ -1,8 +1,9 @@ /* * R8A7740 processor support * - * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011, 2012 Renesas Solutions Corp. * Copyright (C) 2011 Kuninori Morimoto + * Copyright (C) 2012 Nobuhiro Iwamatsu * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -623,15 +624,71 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) generic_handle_irq(intcs_evt2irq(evtcodeas)); } -void __init r8a7740_init_irq(void) +static void __init r8a7740_init_intc(resource_size_t intcs0_start, + unsigned short vect) { - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + void __iomem *intevtsa; + + /* demux using INTEVTSA */ + intevtsa = ioremap_nocache(intcs0_start + 0x100, PAGE_SIZE); + irq_set_handler_data(evt2irq(vect), (void *)intevtsa); + irq_set_chained_handler(evt2irq(vect), intcs_demux); +} + +#ifdef CONFIG_OF +static unsigned short intevtsa_vect; + +#define INTC_RES_MAX 2 +static struct { + struct intc_desc intc_desc; + struct resource intc_res[INTC_RES_MAX]; +} intc_data __initdata; + +static int __init intc_of_init(struct device_node *np, + struct device_node *parent) +{ + int ret, i; + + memset(&intc_data, 0, sizeof(intc_data)); + + for (i = 0; i < INTC_RES_MAX; i++) { + ret = of_address_to_resource(np, i, &intc_data.intc_res[i]); + if (ret < 0) + break; + } + + intc_data.intc_desc.name = (char *)of_node_full_name(np); + intc_data.intc_desc.resource = intc_data.intc_res; + intc_data.intc_desc.num_resources = i; + + ret = of_sh_intc_get_intc(np, &intc_data.intc_desc); + if (ret) + return ret; + of_sh_intc_get_intevtsa_vect(np, &intevtsa_vect); + + register_intc_controller(&intc_data.intc_desc); + return 0; +} + +static const struct of_device_id irq_of_match[] __initconst = { + { .compatible = "renesas,sh_intc", .data = intc_of_init }, + { /*sentinel*/ } +}; + +void __init r8a7740_init_irq_of(void) +{ + of_irq_init(irq_of_match); + + r8a7740_init_intc(0xffd20000, intevtsa_vect); +} +#endif /* CONFIG_OF */ + +void __init r8a7740_init_irq(void) +{ register_intc_controller(&intca_desc); register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); - /* demux using INTEVTSA */ - irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); - irq_set_chained_handler(evt2irq(0xf80), intcs_demux); + r8a7740_init_intc(intcs_resources[0].start, 0xf80); }