From patchwork Thu Nov 22 15:50:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 1783911 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id EE0863FCAE for ; Thu, 22 Nov 2012 15:53:43 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TbZ32-0001HX-1W; Thu, 22 Nov 2012 15:50:40 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TbZ2w-0001Gy-NQ for linux-arm-kernel@lists.infradead.org; Thu, 22 Nov 2012 15:50:36 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MDW00HQ7BZXOCT0@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 23 Nov 2012 00:50:29 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-65-50ae49c5bf0c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 7B.C6.12699.5C94EA05; Fri, 23 Nov 2012 00:50:29 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDW006I1BZY2E70@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 23 Nov 2012 00:50:29 +0900 (KST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 Date: Thu, 22 Nov 2012 16:50:19 +0100 Message-id: <1353599419-24218-1-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.7.10 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFJMWRmVeSWpSXmKPExsVy+t9jAd2jnusCDI790bDY9PgaqwOjx+Yl 9QGMUVw2Kak5mWWpRfp2CVwZ3c8esRZcFqtonDmBuYHxvlAXIyeHhICJRNOpPjYIW0ziwr31 QDYXh5DAIkaJ94fuMkE4m5kk5s04yQpSxSagJvG54RFYh4iAqsTntgXsIEXMAosZJSbMbmLu YuTgEBYIkbi9IQqkhgWoZu6myWC9vAJOEu3nj7FAbJOXeHq/j20CI/cCRoZVjKKpBckFxUnp uUZ6xYm5xaV56XrJ+bmbGME+fCa9g3FVg8UhRgEORiUe3gyDtQFCrIllxZW5hxglOJiVRHhz 9NcFCPGmJFZWpRblxxeV5qQWH2KU5mBREudt9kgJEBJITyxJzU5NLUgtgskycXBKNTDaN0xN ristMGHQ25PY3uzmpih49sJEu4nfdZbt4L0pqXtp6jntRew3fXM0uGeeytd8GlP6U9/ZId4s fsExhUP+k/Jr2iI+3tbwnXxb8UGx1RuujPP2Yis8l3Zd38ZyxnPWvIPffByFP3JbZXN9Xd5/ VH/Cy0nzd8iqX8vx4M7p01lZcNvZ2FCJpTgj0VCLuag4EQCz5aKX3QEAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121122_105035_172499_EBC25C0C X-CRM114-Status: GOOD ( 12.36 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kgene.kim@samsung.com, t.figa@samsung.com, tomasz.figa@gmail.com, kyungmin.park@samsung.com, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Exynos4412 uses different information register for each core. This patch adjusts the bring-up code to take that into account. Signed-off-by: Tomasz Figa Reviewed-by: Kyungmin Park --- arch/arm/mach-exynos/platsmp.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index f93d820..4ca8ff1 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -36,8 +36,22 @@ extern void exynos4_secondary_startup(void); -#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - S5P_INFORM5 : S5P_VA_SYSRAM) +static inline void __iomem *cpu_boot_reg_base(void) +{ + if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) + return S5P_INFORM5; + return S5P_VA_SYSRAM; +} + +static inline void __iomem *cpu_boot_reg(int cpu) +{ + void __iomem *boot_reg; + + boot_reg = cpu_boot_reg_base(); + if (soc_is_exynos4412()) + boot_reg += 4*cpu; + return boot_reg; +} /* * Write pen_release in a way that is guaranteed to be visible to all @@ -84,6 +98,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu) static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; + unsigned long phys_cpu = cpu_logical_map(cpu); /* * Set synchronisation state between this boot processor @@ -99,7 +114,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct * Note that "pen_release" is the hardware CPU ID, whereas * "cpu" is Linux's internal ID. */ - write_pen_release(cpu_logical_map(cpu)); + write_pen_release(phys_cpu); if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { __raw_writel(S5P_CORE_LOCAL_PWR_EN, @@ -133,7 +148,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct smp_rmb(); __raw_writel(virt_to_phys(exynos4_secondary_startup), - CPU1_BOOT_REG); + cpu_boot_reg(phys_cpu)); gic_raise_softirq(cpumask_of(cpu), 0); if (pen_release == -1) @@ -181,6 +196,8 @@ static void __init exynos_smp_init_cpus(void) static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { + int i; + if (!soc_is_exynos5250()) scu_enable(scu_base_addr()); @@ -190,8 +207,9 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(virt_to_phys(exynos4_secondary_startup), - CPU1_BOOT_REG); + for (i = 1; i < max_cpus; ++i) + __raw_writel(virt_to_phys(exynos4_secondary_startup), + cpu_boot_reg(cpu_logical_map(i))); } struct smp_operations exynos_smp_ops __initdata = {