From patchwork Fri Nov 23 00:49:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Vorontsov X-Patchwork-Id: 1793301 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 9BDCB3FC64 for ; Fri, 23 Nov 2012 00:57:27 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TbhWU-0006W5-2e; Fri, 23 Nov 2012 00:53:38 +0000 Received: from mail-ob0-f177.google.com ([209.85.214.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TbhWK-0006TH-Bv for linux-arm-kernel@lists.infradead.org; Fri, 23 Nov 2012 00:53:32 +0000 Received: by mail-ob0-f177.google.com with SMTP id eh20so8362162obb.36 for ; Thu, 22 Nov 2012 16:53:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=El1rkNr3e927FjI/rCbsbZMZJ/i4mdMxhto/RGJk6HI=; b=mn6p8UV8Ehj4R+u1dEBhsbkK/ex3l6KpPyTe4CazvhdtTXmxfLYiOnr49/k0aS589h Hk1MKsYtDQ4x8LuGRqlBcmzlXxa1/uXkaHd5/ywQuhCERaIudrkl80ACucObyr3Gomja zWv8mQ6ltNUMz48zsDoHUcINNDDnGFoF9JqhjjbOPdxH7bHVQel2p0BG5APc0y9zcN4D nL8ZsiPq2uLYr/Dhif/J42wDCrXv90Fu8YPkrF+K1Q+0ELxQTiGQC1+KHcnhHKvQOV5K 2UQURzmvs/2XorA64tcwCKXWnSQxM0/+KsaL8nxoR2fd/YXuxc7W0ZIgutWyOsSj13lW KaTQ== Received: by 10.60.32.193 with SMTP id l1mr1573690oei.114.1353632006799; Thu, 22 Nov 2012 16:53:26 -0800 (PST) Received: from localhost (ip-64-134-239-153.public.wayport.net. [64.134.239.153]) by mx.google.com with ESMTPS id q4sm4476274obz.3.2012.11.22.16.53.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 16:53:26 -0800 (PST) From: Anton Vorontsov To: Andrew Morton Subject: [PATCH 01/10] ARM: mach-rpc: Don't register FIQs with genirq Date: Thu, 22 Nov 2012 16:49:54 -0800 Message-Id: <1353631803-4853-1-git-send-email-anton.vorontsov@linaro.org> X-Mailer: git-send-email 1.8.0 In-Reply-To: <20121123003849.GA973@lizard.mcd25758.sjc.wayport.net> References: <20121123003849.GA973@lizard.mcd25758.sjc.wayport.net> X-Gm-Message-State: ALoCoQllarkPyquxwC6jNkq6Ym1CHWq3nrhWN3TXbm4A1GmFOtkY+teFj6TFNTjeNhlQRtkmUhYc X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121122_195328_501607_AD1A75AD X-CRM114-Status: GOOD ( 14.09 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-kernel@lists.linaro.org, Russell King , patches@linaro.org, linux-kernel@vger.kernel.org, John Stultz , Jason Wessel , kernel-team@android.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org mach-rps registers FIQ controller with genirq, which makes no sense: these FIQs cannot be routed to IRQs, so there is no need to register it with genirq. This effectively makes FIQ_START irrelevant. Signed-off-by: Anton Vorontsov --- arch/arm/mach-rpc/dma.c | 4 ++-- arch/arm/mach-rpc/include/mach/irqs.h | 5 +++++ arch/arm/mach-rpc/irq.c | 19 ++++--------------- 3 files changed, 11 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 85883b2..4a525be 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c @@ -289,13 +289,13 @@ static void floppy_enable_dma(unsigned int chan, dma_t *dma) set_fiq_handler(fiqhandler_start, fiqhandler_length); set_fiq_regs(®s); - enable_fiq(fdma->fiq); + iomd_unmask_fiq(fdma->fiq); } static void floppy_disable_dma(unsigned int chan, dma_t *dma) { struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); - disable_fiq(fdma->fiq); + iomd_mask_fiq(fdma->fiq); release_fiq(&fh); } diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h index 6868e17..f27ead1 100644 --- a/arch/arm/mach-rpc/include/mach/irqs.h +++ b/arch/arm/mach-rpc/include/mach/irqs.h @@ -37,6 +37,11 @@ #define FIQ_EXPANSIONCARD 6 #define FIQ_FORCE 7 +#ifndef __ASSEMBLY__ +extern void iomd_mask_fiq(int fiq); +extern void iomd_unmask_fiq(int fiq); +#endif + /* * This is the offset of the FIQ "IRQ" numbers */ diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index 3e4fa84..a4221b3 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -89,30 +89,24 @@ static struct irq_chip iomd_dma_chip = { .irq_unmask = iomd_unmask_irq_dma, }; -static void iomd_mask_irq_fiq(struct irq_data *d) +void iomd_mask_fiq(int fiq) { unsigned int val, mask; - mask = 1 << (d->irq & 7); + mask = 1 << (fiq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val & ~mask, IOMD_FIQMASK); } -static void iomd_unmask_irq_fiq(struct irq_data *d) +void iomd_unmask_fiq(int fiq) { unsigned int val, mask; - mask = 1 << (d->irq & 7); + mask = 1 << (fiq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val | mask, IOMD_FIQMASK); } -static struct irq_chip iomd_fiq_chip = { - .irq_ack = iomd_mask_irq_fiq, - .irq_mask = iomd_mask_irq_fiq, - .irq_unmask = iomd_unmask_irq_fiq, -}; - extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end; void __init rpc_init_irq(void) @@ -155,11 +149,6 @@ void __init rpc_init_irq(void) handle_level_irq); set_irq_flags(irq, flags); break; - - case 64 ... 71: - irq_set_chip(irq, &iomd_fiq_chip); - set_irq_flags(irq, IRQF_VALID); - break; } }