From patchwork Fri Nov 30 15:41:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1825601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 7D146DF24C for ; Fri, 30 Nov 2012 15:44:43 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TeSiU-0006sr-CK; Fri, 30 Nov 2012 15:41:26 +0000 Received: from mail-gg0-f177.google.com ([209.85.161.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TeSiQ-0006s1-Sm for linux-arm-kernel@lists.infradead.org; Fri, 30 Nov 2012 15:41:23 +0000 Received: by mail-gg0-f177.google.com with SMTP id y3so76944ggc.36 for ; Fri, 30 Nov 2012 07:41:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=bKvTIkIEwNctosS6uqejJya2wsFIaPKFJblvO/dBgR4=; b=lcAfrCi+Fjn5eCO41CYRgVq51gXGur1+/zmA+vbCMnVlowLFybvZtsgwjaBvD7UTjd qF2aOV3corw2xLC10Y6p/tuC5gkeYVaWALqdLPSZCtB9lBAVAUvdBAOq7L8RQIp4Shiz C6zviA7ZS2hBwAYM3eyWYmC5pwWdAijUYn7NJZxxpPiWqQBCo94mTg1cvFx+P9INJFKp dbRGMJvS9m+rwerW4fCIDIfoPXUuM3KdnPmUz4gzEiokIHZsxI0HLAe+qCmGoR6fLLpT uMh+ZqEw2t7DuRuZEJYBvzJdDgDspB07+jRYoC0YWnqPM4mZsaO4r+FtalmTyzvp62aY vwqw== Received: by 10.236.154.165 with SMTP id h25mr1594337yhk.38.1354290081627; Fri, 30 Nov 2012 07:41:21 -0800 (PST) Received: from localhost.localdomain (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id k49sm5147398yhj.13.2012.11.30.07.41.20 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Nov 2012 07:41:20 -0800 (PST) From: Christoffer Dall To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] ARM: Factor out cpuid implementor and part number Date: Fri, 30 Nov 2012 10:41:13 -0500 Message-Id: <1354290073-55801-1-git-send-email-c.dall@virtualopensystems.com> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQnbvb5Lg+3TI603K6NPCwMkvUWQWcyoTj5CxtJduQH4AfXuLn9mkBSRRKyhV/gfW7tamewV X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121130_104123_033247_DAF7234B X-CRM114-Status: GOOD ( 17.37 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.161.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Christoffer Dall , Will Deacon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Decoding the implementor and part number of the CPU id in the CPU ID register is needed by KVM, so we factor it out to share the code. Cc: Will Deacon Signed-off-by: Christoffer Dall --- Changes since v2: - Take implementor as argument to read_cpuid_part_number Changes since v1: - Accidentally pointed to an old file, this one has more consistent naming of the cpu implementor and part number defines. arch/arm/include/asm/cputype.h | 34 ++++++++++++++++++++++++++++++++++ arch/arm/kernel/perf_event_cpu.c | 33 +++++++++++++++++---------------- 2 files changed, 51 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cb47d28..3e6cd4e 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -51,6 +51,22 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_INTEL 0x69 + +#define ARM_CPU_PART_ARM1136 0xB360 +#define ARM_CPU_PART_ARM1156 0xB560 +#define ARM_CPU_PART_ARM1176 0xB760 +#define ARM_CPU_PART_ARM11MPCORE 0xB020 +#define ARM_CPU_PART_CORTEX_A8 0xC080 +#define ARM_CPU_PART_CORTEX_A9 0xC090 +#define ARM_CPU_PART_CORTEX_A5 0xC050 +#define ARM_CPU_PART_CORTEX_A15 0xC0F0 +#define ARM_CPU_PART_CORTEX_A7 0xC070 + +#define ARM_CPU_PART_XSCALE1 0x1 +#define ARM_CPU_PART_XSCALE2 0x2 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -61,6 +77,24 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ +read_cpuid_part_number(unsigned int implementor) +{ + switch (implementor) { + case ARM_CPU_IMP_ARM: + return (read_cpuid_id() & 0xFFF0); + case ARM_CPU_IMP_INTEL: + return (read_cpuid_id() >> 13) & 0x7; + default: + return 0; + } +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 9a4f630..0ec7b54 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -202,47 +202,48 @@ static int __devinit probe_current_pmu(struct arm_pmu *pmu) { int cpu = get_cpu(); unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number; int ret = -ENODEV; pr_info("probing PMU on CPU %d\n", cpu); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == ARM_CPU_IMP_ARM) { + part_number = read_cpuid_part_number(implementor); switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case ARM_CPU_PART_ARM1136: + case ARM_CPU_PART_ARM1156: + case ARM_CPU_PART_ARM1176: ret = armv6pmu_init(pmu); break; - case 0xB020: /* ARM11mpcore */ + case ARM_CPU_PART_ARM11MPCORE: ret = armv6mpcore_pmu_init(pmu); break; - case 0xC080: /* Cortex-A8 */ + case ARM_CPU_PART_CORTEX_A8: ret = armv7_a8_pmu_init(pmu); break; - case 0xC090: /* Cortex-A9 */ + case ARM_CPU_PART_CORTEX_A9: ret = armv7_a9_pmu_init(pmu); break; - case 0xC050: /* Cortex-A5 */ + case ARM_CPU_PART_CORTEX_A5: ret = armv7_a5_pmu_init(pmu); break; - case 0xC0F0: /* Cortex-A15 */ + case ARM_CPU_PART_CORTEX_A15: ret = armv7_a15_pmu_init(pmu); break; - case 0xC070: /* Cortex-A7 */ + case ARM_CPU_PART_CORTEX_A7: ret = armv7_a7_pmu_init(pmu); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; + } else if (implementor == ARM_CPU_IMP_INTEL) { + part_number = read_cpuid_part_number(implementor); switch (part_number) { - case 1: + case ARM_CPU_PART_XSCALE1: ret = xscale1pmu_init(pmu); break; - case 2: + case ARM_CPU_PART_XSCALE2: ret = xscale2pmu_init(pmu); break; }