From patchwork Mon Dec 3 17:52:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 1834631 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 6F46CDF2F9 for ; Mon, 3 Dec 2012 17:55:39 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TfaCd-0001Le-2j; Mon, 03 Dec 2012 17:53:11 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TfaCK-0001Ia-1K for linux-arm-kernel@lists.infradead.org; Mon, 03 Dec 2012 17:52:55 +0000 Received: from mudshark.cambridge.arm.com (mudshark.cambridge.arm.com [10.1.79.58]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id qB3Hqh53002348; Mon, 3 Dec 2012 17:52:43 GMT Received: by mudshark.cambridge.arm.com (Postfix, from userid 1000) id 77ABDC2A9C; Mon, 3 Dec 2012 17:52:42 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 2/2] ARM: SMP support for mach-virt Date: Mon, 3 Dec 2012 17:52:40 +0000 Message-Id: <1354557160-20144-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1354557160-20144-1-git-send-email-will.deacon@arm.com> References: <1354557160-20144-1-git-send-email-will.deacon@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121203_125252_528224_3270DB5F X-CRM114-Status: GOOD ( 27.48 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.96.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: marc.zyngier@arm.com, xen-arm@lists.xen.org, mark.rutland@arm.com, Will Deacon , arnd@arnd.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Marc Zyngier This patch adds support for SMP to mach-virt. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm/mach-virt/Makefile | 1 + arch/arm/mach-virt/headsmp.S | 38 ++++++++ arch/arm/mach-virt/platsmp.c | 205 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-virt/virt.c | 6 ++ 4 files changed, 250 insertions(+) create mode 100644 arch/arm/mach-virt/headsmp.S create mode 100644 arch/arm/mach-virt/platsmp.c diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile index 7ddbfa6..9ce8a28 100644 --- a/arch/arm/mach-virt/Makefile +++ b/arch/arm/mach-virt/Makefile @@ -3,3 +3,4 @@ # obj-y := virt.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-virt/headsmp.S b/arch/arm/mach-virt/headsmp.S new file mode 100644 index 0000000..e27afb0 --- /dev/null +++ b/arch/arm/mach-virt/headsmp.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2012 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include + + __INIT + +/* + * This provides a "holding pen" into which all secondary cores are held + * until we're ready for them to initialise. + */ +ENTRY(virt_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release +ENDPROC(virt_secondary_startup) diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c new file mode 100644 index 0000000..fe02f51 --- /dev/null +++ b/arch/arm/mach-virt/platsmp.c @@ -0,0 +1,205 @@ +/* + * Dummy Virtual Machine - does what it says on the tin. + * + * SMP operations, shamelessly stolen from: + * arch/arm64/kernel/smp.c + * + * Copyright (C) 2012 ARM Ltd + * Author: Catalin Marinas + * Author: Will Deacon + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern void virt_secondary_startup(void); + +static DEFINE_RAW_SPINLOCK(boot_lock); +static phys_addr_t cpu_release_addr[NR_CPUS]; + +/* + * Write secondary_holding_pen_release in a way that is guaranteed to be + * visible to all observers, irrespective of whether they're taking part + * in coherency or not. This is necessary for the hotplug code to work + * reliably. + */ +static void __cpuinit write_pen_release(int val) +{ + void *start = (void *)&pen_release; + unsigned long size = sizeof(pen_release); + + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area(start, size); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +/* + * Enumerate the possible CPU set from the device tree. + */ +static void __init virt_smp_init_cpus(void) +{ + const char *enable_method; + struct device_node *dn = NULL; + int cpu = 0; + u32 release_addr; + + while ((dn = of_find_node_by_type(dn, "cpu"))) { + if (cpu >= NR_CPUS) + goto next; + + /* + * We currently support only the "spin-table" enable-method. + */ + enable_method = of_get_property(dn, "enable-method", NULL); + if (!enable_method || strcmp(enable_method, "spin-table")) { + pr_err("CPU %d: missing or invalid enable-method property: %s\n", + cpu, enable_method); + goto next; + } + + /* + * Determine the address from which the CPU is polling. + */ + if (of_property_read_u32(dn, "cpu-release-addr", &release_addr)) { + pr_err("CPU %d: missing or invalid cpu-release-addr property\n", + cpu); + goto next; + } + + cpu_release_addr[cpu] = release_addr; + set_cpu_possible(cpu, true); +next: + cpu++; + } + + /* sanity check */ + if (cpu > NR_CPUS) + pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n", + cpu, NR_CPUS); + + set_smp_cross_call(gic_raise_softirq); +} + +static void __init virt_smp_prepare_cpus(unsigned int max_cpus) +{ + int cpu; + void **release_addr; + unsigned int ncores = num_possible_cpus(); + + /* + * are we trying to boot more cores than exist? + */ + if (max_cpus > ncores) + max_cpus = ncores; + + /* + * Initialise the present map (which describes the set of CPUs + * actually populated at the present time) and release the + * secondaries from the bootloader. + */ + for_each_possible_cpu(cpu) { + if (max_cpus == 0) + break; + + if (!cpu_release_addr[cpu]) + continue; + + release_addr = __va(cpu_release_addr[cpu]); + release_addr[0] = (void *)__pa(virt_secondary_startup); + smp_wmb(); + __cpuc_flush_dcache_area(release_addr, sizeof(release_addr[0])); + outer_clean_range(__pa(release_addr), __pa(release_addr+1)); + + set_cpu_present(cpu, true); + max_cpus--; + } +} + +static int __cpuinit virt_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + raw_spin_lock(&boot_lock); + + /* + * Update the pen release flag. + */ + write_pen_release(cpu); + + /* + * Send the secondary CPU a soft interrupt, causing the + * secondaries to read pen_release. + */ + gic_raise_softirq(cpumask_of(cpu), 0); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + if (pen_release == -1UL) + break; + udelay(10); + } + + /* + * Now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + raw_spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __cpuinit virt_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + /* + * Synchronise with the boot thread. + */ + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); +} + +struct smp_operations __initdata virt_smp_ops = { + .smp_init_cpus = virt_smp_init_cpus, + .smp_prepare_cpus = virt_smp_prepare_cpus, + .smp_secondary_init = virt_secondary_init, + .smp_boot_secondary = virt_boot_secondary, +}; diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c index 174b9da..d764835 100644 --- a/arch/arm/mach-virt/virt.c +++ b/arch/arm/mach-virt/virt.c @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -56,10 +57,15 @@ static struct sys_timer virt_timer = { .init = virt_timer_init, }; +#ifdef CONFIG_SMP +extern struct smp_operations virt_smp_ops; +#endif + DT_MACHINE_START(VIRT, "Dummy Virtual Machine") .init_irq = gic_init_irq, .handle_irq = gic_handle_irq, .timer = &virt_timer, .init_machine = virt_init, + .smp = smp_ops(virt_smp_ops), .dt_compat = virt_dt_match, MACHINE_END